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1. 发明授权

US06228745B1 Selective reduction of sidewall slope on isolation edge 失效
标题翻译：隔离边缘侧壁倾斜的选择性减小
公开(公告)号：US06228745B1
公开(公告)日：2001-05-08
申请号：US09460134
申请日：1999-12-13
申请人： Donald C. Wheeler , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
发明人： Donald C. Wheeler , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S438/947
摘要： Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.
摘要翻译：公开了一种半导体结构，其包括在半导体衬底中形成的源极注入和漏极注入的晶体管。晶体管还包括栅电极，栅极氧化物和有源区。源极注入和漏极注入位于所述有源区的相对侧，并且所述栅极氧化物和栅电极位于所述有源区的顶部。晶体管还包括与所述有源区相邻的两个沟槽隔离，其中所述沟槽隔离位于所述有源区的相对侧，使得每个沟槽的侧壁用作与所述有源区的界面，所述沟槽的至少一个侧壁用作与所述有源区的界面的隔离具有倾斜的90°至150°之间的斜率，所述沟槽隔离和源极注入和漏极注入在四个侧面上包围所述有源区。

2. 发明授权

US06015991A Asymmetrical field effect transistor 失效
标题翻译：非对称场效应晶体管
公开(公告)号：US06015991A
公开(公告)日：2000-01-18
申请号：US820401
申请日：1997-03-12
申请人： Donald C. Wheeler , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
发明人： Donald C. Wheeler , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Rebecca D. Mih
IPC分类号： H01L21/027 , H01L21/266 , H01L21/3213 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/423 , H01L29/78 , H01L29/02
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/32139 , H01L29/42376 , H01L29/66545 , H01L29/66659 , H01L29/7835 , H01L21/0274
摘要： Disclosed is an asymmetric field effect transistor which comprises a first region serving as source, a second region serving as drain, a thin gate oxide and a gate electrode. The gate electrode is asymmetric and one of its sidewalls is sloped. The second region extends underneath said sloped sidewall. The part of said second region which extends underneath said gate electrode is less doped than the remaining part of said second region. Furthermore, said second region has a sloped junction edge underneath said gate electrode.
摘要翻译：公开了一种非对称场效应晶体管，其包括用作源极的第一区域，用作漏极的第二区域，薄栅极氧化物和栅电极。栅电极是不对称的，其侧壁之一是倾斜的。第二区域在所述倾斜侧壁的下方延伸。在所述栅电极下方延伸的所述第二区域的部分比所述第二区域的剩余部分掺杂少。此外，所述第二区域在所述栅电极下方具有倾斜的接合边缘。

3. 发明授权

US5985492A Multi-phase mask 失效
标题翻译：多相面罩
公开(公告)号：US5985492A
公开(公告)日：1999-11-16
申请号：US10611
申请日：1998-01-22
申请人： Donald C. Wheeler , Jack A. Mandelman , Rebecca D. Mih
发明人： Donald C. Wheeler , Jack A. Mandelman , Rebecca D. Mih
IPC分类号： G03F1/28 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F1/28
摘要： A photomask and a method for using the photomask to make dimensionally controlled resist patterns are provided. A wafer having a resist coating thereon is exposed using the mask of the invention under specially controlled defocus conditions to provide the dimensionally controlled resist pattern profile. The mask which comprises multiple phase shifter means on one side of at least one of the light shielding patterns on the mask provides light passing through the mask having multiple phases on that side of the light shielding material which produces a dimensionally controlled resist pattern profile.
摘要翻译：提供光掩模和使用光掩模来制造尺寸控制的抗蚀剂图案的方法。在其上具有抗蚀剂涂层的晶片在特殊控制的散焦条件下使用本发明的掩模曝光以提供尺寸控制的抗蚀剂图案轮廓。在掩模上的至少一个遮光图案的一侧包括多个移相器装置的掩模提供通过遮光材料的该侧的多个相位的光的光，其产生尺寸控制的抗蚀剂图形轮廓。

4. 发明授权

US06809372B2 Flash memory structure using sidewall floating gate 失效
标题翻译：闪存结构采用侧壁浮栅
公开(公告)号：US06809372B2
公开(公告)日：2004-10-26
申请号：US09756177
申请日：2001-01-09
申请人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Donald C. Wheeler
发明人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Donald C. Wheeler
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.
摘要翻译：闪速存储器和形成闪速存储器的方法包括在衬底上形成多晶硅字线，所述字线具有第一和第二侧壁，所述第一侧壁相对于所述衬底的表面是渐缩的，以具有倾斜角和所述第二侧壁具有大于所述第一侧壁的倾斜角的倾斜角。此后，在第二侧壁上形成多晶硅间隔物，同时去除第一侧壁上的多晶硅。多晶硅间隔物形成浮动栅极，其通过第二侧壁在多个侧面上被包围。

5. 发明授权

US06252271B1 Flash memory structure using sidewall floating gate and method for forming the same 失效
公开(公告)号：US06252271B1
公开(公告)日：2001-06-26
申请号：US09097515
申请日：1998-06-15
申请人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Donald C. Wheeler
发明人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Donald C. Wheeler
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.

6. 发明授权

US07804148B2 Opto-thermal mask including aligned thermal dissipative layer, reflective layer and transparent capping layer 失效
标题翻译：光热掩模包括对准的热耗散层，反射层和透明覆盖层
公开(公告)号：US07804148B2
公开(公告)日：2010-09-28
申请号：US11355799
申请日：2006-02-16
申请人： Louis L. Hsu , Jack A. Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
发明人： Louis L. Hsu , Jack A. Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
IPC分类号： H01L23/58 , H01L31/058 , H01L31/02 , H01L31/0232 , H01L31/024 , H01L21/033 , H01L21/00
CPC分类号： H01L21/268 , H01L21/84 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.
摘要翻译：光热退火掩模层叠层包括位于衬底上的散热层。反射层位于热耗散层上。可以具有约10至约100埃厚度的透明覆盖层位于反射层上。光热退火掩模层可以用作场效应器件中的栅电极。

7. 发明申请

US20090212341A1 SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
标题翻译：半导体金属氧化物半导体场效应晶体管
公开(公告)号：US20090212341A1
公开(公告)日：2009-08-27
申请号：US12034899
申请日：2008-02-21
申请人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
发明人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/66795 , H01L29/7841 , H01L29/7853
摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.
摘要翻译：在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。

8. 发明授权

US06617702B2 Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate 有权
标题翻译：半导体器件利用对准标记来全面对准半导体衬底的正面和背面
公开(公告)号：US06617702B2
公开(公告)日：2003-09-09
申请号：US09769080
申请日：2001-01-25
申请人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
发明人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
IPC分类号： H01L23544
CPC分类号： H01L23/48 , H01L21/8221 , H01L23/544 , H01L24/48 , H01L24/73 , H01L27/0694 , H01L2223/54473 , H01L2224/05599 , H01L2224/16225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01077 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , Y10T29/49133 , Y10T29/49155 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
摘要翻译：本发明提供了在一个或多个基板的正面和背面上制造或结合到其上的微电子电路系统，例如通信设备和芯片，以提供通过一个或多个基板的电路系统之间的无线通信。在一个实施例中，位于衬底的相对侧上的两个电路系统被对准以提供通过衬底的两个电路系统之间的无线通信。在另一个实施例中，位于一个或多个基板上的通信设备被对准以通过一个或多个基板来提供通信设备之间的无线通信。在另一个实施例中，位于透明基板的相对侧上的两个芯片被对准以提供通过透明基板的两个芯片之间的无线通信。

9. 发明授权

US06410369B1 Soi-body selective link method and apparatus 失效
标题翻译：单体选择性联动方法及装置
公开(公告)号：US06410369B1
公开(公告)日：2002-06-25
申请号：US09591511
申请日：2000-06-12
申请人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
发明人： Roy Childs Flaker , Louis L. Hsu , Fariborz Assaderaghi , Jack A. Mandelman
IPC分类号： H01L2100
CPC分类号： H01L27/1104 , H01L27/1203
摘要： A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.
摘要翻译：绝缘体上硅（SOI）结构及其制造方法包括具有形成在隔离氧化层上的原始厚度尺寸的硅层的SOI晶片。在硅层中形成至少两个至少两个SOI场效应晶体管（PFET）的p型体。在硅层中还形成至少两个至少两个SOI场效应晶体管（NFET）的n型体。最后，在隔离氧化层附近的SOI晶片的硅层中形成SOI本体连接，用于选择性地连接p型SOI FET或n型SOI FET的所需体，并允许连接体浮置。

10. 发明授权

US06222244B1 Electrically blowable fuse with reduced cross-sectional area 失效
标题翻译：具有减小横截面积的可电熔保险丝
公开(公告)号：US06222244B1
公开(公告)日：2001-04-24
申请号：US09093903
申请日：1998-06-08
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译：半导体保险丝位于用于连接布线的导体之间。保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

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