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1. 发明授权

US5175856A Computer with integrated hierarchical representation (IHR) of program wherein IHR file is available for debugging and optimizing during target execution 失效
标题翻译：具有IHR文件的程序集成分层代码（IHR）的计算机在目标执行过程中可用于调试和优化
公开(公告)号：US5175856A
公开(公告)日：1992-12-29
申请号：US572043
申请日：1990-08-23
申请人： Don A. Van Dyke , Timothy J. Cramer , James C. Rasbold , Kelly T. O'Hair , David M. Cox , David A. Seberger , Linda J. O'Gara , Jon A. Masamitsu , Robert E. Strout, II , Ashok Chandramouli
发明人： Don A. Van Dyke , Timothy J. Cramer , James C. Rasbold , Kelly T. O'Hair , David M. Cox , David A. Seberger , Linda J. O'Gara , Jon A. Masamitsu , Robert E. Strout, II , Ashok Chandramouli
IPC分类号： G06F9/06 , G06F9/44 , G06F9/45 , G06F11/28 , G06F11/36 , G06F12/02 , G06F12/08 , G06F12/12
CPC分类号： G06F8/41 , G06F11/3664 , G06F12/023 , G06F12/08 , G06F12/12 , G06F8/433 , G06F8/445 , G06F8/45
摘要： A modular compilation system that utilizes a fully integrated hierarchical representation as a common intermediate representation to compile source code programs written in one or more procedural programming languages into an executable object code file. The structure of the integrated common intermediate representation supports machine-independent optimizations, as well as machine-dependent optimizations, and also supports source-level debugging of the executable object code file. The integrated hierarchical representation (IHR) is language independent and is shared by all of the components of the software development system, including the debugger.
摘要翻译：一种模块化编译系统，其利用完全集成的层次表示作为公共中间表示，以将一个或多个过程编程语言编写的源代码程序编译成可执行目标代码文件。集成通用中间代码的结构支持独立于机器的优化，以及依赖于机器的优化，还支持可执行对象代码文件的源代码级调试。集成分层表示（IHR）是语言无关的，由软件开发系统的所有组件（包括调试器）共享。

2. 发明授权

US06195676B1 Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes 失效
标题翻译：用于实现进程分配调度的多处理器操作系统程序中用户端调度的方法和装置
公开(公告)号：US06195676B1
公开(公告)日：2001-02-27
申请号：US08003000
申请日：1993-01-11
申请人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
发明人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
IPC分类号： G06F946
CPC分类号： G06F9/30149 , G06F8/41 , G06F8/433 , G06F8/445 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/4881 , G06F11/3664 , G06F12/023 , G06F12/08 , G06F12/12 , G06F15/17381 , G06F15/8076 , G06F15/8092
摘要： An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
摘要翻译：具有共享公用存储器的多个紧密耦合处理器的高度并行多处理器系统的集成软件架构有效地控制与这种多处理器系统上的程序的接口和执行。软件架构结合了对称集成的多线程操作系统和集成并行用户环境。操作系统通过允许每个处理器访问存储在公共存储器中的操作系统的单个映像来分布式地实现用于进程和资源的调度的基于无政府状态的调度模型，该公共存储器在公共操作系统共享资源集合上操作。用户环境为多个程序开发工具提供了通用的可视化表示，为多线程用户程序提供编译，执行和调试功能，并假设并行性作为标准操作模式。

3. 发明授权

US5179702A System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling 失效
标题翻译：用于使用基于无政府状态的调度器来控制并行执行线程调度的高度并行多处理器的系统和方法
公开(公告)号：US5179702A
公开(公告)日：1993-01-12
申请号：US537466
申请日：1990-06-11
申请人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
发明人： George A. Spix , Diane M. Wengelski , Stuart W. Hawkinson , Mark D. Johnson , Jeremiah D. Burke , Keith J. Thompson , Gregory G. Gaertner , Giacomo G. Brussino , Richard E. Hessel , David M. Barkai , Steve S. Chen , Steven G. Oslon , Robert E. Strout, II , Jon A. Masamitsu , David M. Cox , Linda J. O'Gara , Kelly T. O'Hair , David A. Seberger , James C. Rasbold , Timothy J. Cramer , Don A. Van Dyke , Ashok Chandramouli
IPC分类号： G06F9/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F9/46 , G06F9/48 , G06F11/28 , G06F11/36 , G06F12/02 , G06F12/08 , G06F12/12 , G06F15/16 , G06F15/167 , G06F15/173 , G06F15/78 , G06F15/80
CPC分类号： G06F9/30149 , G06F11/3664 , G06F12/023 , G06F12/08 , G06F12/12 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/41 , G06F8/433 , G06F8/445 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/4881
摘要： An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
摘要翻译：具有共享公用存储器的多个紧密耦合处理器的高度并行多处理器系统的集成软件架构有效地控制与这种多处理器系统上的程序的接口和执行。软件架构结合了对称集成的多线程操作系统和集成并行用户环境。操作系统通过允许每个处理器访问存储在公共存储器中的操作系统的单个映像来分布式地实现用于进程和资源的调度的基于无政府状态的调度模型，该公共存储器在公共操作系统共享资源集合上操作。用户环境为多个程序开发工具提供了通用的可视化表示，为多线程用户程序提供编译，执行和调试功能，并假设并行性作为标准操作模式。

4. 发明授权

US6018799A Method, apparatus and computer program product for optimizing registers in a stack using a register allocator 失效
标题翻译：用于使用寄存器分配器优化堆栈中的寄存器的方法，装置和计算机程序产品
公开(公告)号：US6018799A
公开(公告)日：2000-01-25
申请号：US121167
申请日：1998-07-22
申请人： David R. Wallace , David M. Cox , Serguei V. Morosov , David A. Seberger , Serguei L. Wenitsky
发明人： David R. Wallace , David M. Cox , Serguei V. Morosov , David A. Seberger , Serguei L. Wenitsky
IPC分类号： G06F9/34 , G06F9/318 , G06F9/45 , G06F12/04
CPC分类号： G06F8/441 , G06F8/443
摘要： Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack. The invention operates by transforming a three-operand instruction, within a compiler's intermediate representation, to one or more fewer-than-three-operand instructions. The invention also transforms the instruction's operand addressing from an access to a pseudo-named register to an access to a stack register through stack offset into a register stack. The invention also determines the register stack state at each instruction responsive to register stack permutations and maps the stack offset accordingly for each subsequent access to a stack register.
摘要翻译：公开了装置，方法和计算机程序产品，其使得编译器能够生成有效代码来访问寄存器堆栈上的堆栈寄存器。本发明通过将编译器的中间表示中的三操作数指令变换成一个或多个少于三个操作数的指令来进行操作。本发明还将指令的操作数寻址从访问伪命名寄存器转换为通过堆栈偏移到堆栈寄存器的访问到寄存器堆栈。本发明还响应于寄存器堆栈排列确定每个指令处的寄存器堆栈状态，并相应地映射堆栈偏移量，以便每次后续访问堆栈寄存器。

5. 发明授权

US5193192A Vectorized LR parsing of computer programs 失效
标题翻译：计算机程序的向量化LR解析
公开(公告)号：US5193192A
公开(公告)日：1993-03-09
申请号：US571502
申请日：1990-08-23
申请人： David A. Seberger
发明人： David A. Seberger
IPC分类号： A47G1/06 , B44C5/02 , G06F9/44 , G06F9/45 , G06F11/36 , G06F12/02 , G06F12/08 , G06F12/12
CPC分类号： G06F8/427 , B44C5/02 , G06F12/023 , G06F12/08 , G06F12/12 , G06F8/41 , G06F8/433 , G06F8/445 , G06F8/45 , Y10S707/99942
摘要： A parser for parsing computer programs in a compiler has parsing tables arranged as linear vectors. In a reduction portion of the parser, a production table and a lookahead set table have paired entries at identical address offsets such that a one-to-one relationship exists between each lookahead set in the lookahead set table and the representation of the lookahead set in the lookahead set table. In a read transition portion of the parser, an entrance symbol table has entries paired with transition state representations and each pair being at an identical address offset in the respective tables. For a reduction or read transition operation, the lookahead set table or the entrance symbol table is scanned to find the appropriate entry. Once the appropriate entry is found, the production table or the transition state table is addressed using the offset of the appropriate entry found during the scanning process.
摘要翻译：用于在编译器中解析计算机程序的解析器具有排列成线性向量的解析表。在解析器的缩减部分中，生产表和前瞻集合表具有相同地址偏移处的配对条目，使得在前瞻集合表中设置的每个前瞻头与在前置集合表示中存在一对一关系先行设定表。在解析器的读取转换部分中，入口符号表具有与过渡状态表示配对的条目，并且每对在各个表中具有相同的地址偏移。对于缩小或读取转换操作，扫描前瞻集合表或入口符号表以找到适当的条目。找到适当的条目后，使用扫描过程中找到的适当条目的偏移来寻址生产表或过渡状态表。

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