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1. 发明授权

US07015153B1 Method for forming a layer using a purging gas in a semiconductor process 失效
标题翻译：在半导体工艺中使用吹扫气体形成层的方法
公开(公告)号：US07015153B1
公开(公告)日：2006-03-21
申请号：US10969634
申请日：2004-10-20
申请人： Dina H. Triyoso , Olubunmi O. Adetutu , David C. Gilmer , Darrell Roan , James K. Schaeffer , Philip J. Tobin , Hsing H. Tseng
发明人： Dina H. Triyoso , Olubunmi O. Adetutu , David C. Gilmer , Darrell Roan , James K. Schaeffer , Philip J. Tobin , Hsing H. Tseng
IPC分类号： H01L21/31
CPC分类号： C23C14/0057 , C23C16/30 , C23C16/45527 , H01L21/28229 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.
摘要翻译：一种用于形成半导体器件的至少一部分的方法包括提供半导体衬底，使第一前体气体流过衬底以形成覆盖半导体衬底的第一含金属层，并且在完成所述第一前体气体流动步骤使第一含氘吹扫气体流过第一含金属层，将氘掺入第一含金属层并且还吹扫第一前体气体。该方法还可以包括使第二前体气体流过第一含金属层以与第一含金属层反应以形成含金属化合物的层，并将第二含氘的净化气体流过含金属化合物的层层将氘并入含金属化合物的层中并且还吹扫第二前体气体。

2. 发明授权

US07868389B2 Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities 有权
标题翻译：电子器件包括含有含有一种或多种杂质的含金属层的栅电极
公开(公告)号：US07868389B2
公开(公告)日：2011-01-11
申请号：US11928314
申请日：2007-10-30
申请人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
发明人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823842
摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
摘要翻译：可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数与没有含硼物质的含金属栅电极相比。

3. 发明授权

US07432164B2 Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same 有权
标题翻译：包括具有反掺杂沟道区的晶体管的半导体器件及其形成方法
公开(公告)号：US07432164B2
公开(公告)日：2008-10-07
申请号：US11342025
申请日：2006-01-27
申请人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
发明人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
IPC分类号： H01L21/8236 , H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823842
摘要： A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.
摘要翻译：一种制造半导体器件的方法包括提供第一衬底区域和第二衬底区域，其中第一衬底区域的至少一部分具有第一导电类型，并且第二衬底区域的至少一部分具有不同的第二导电类型从第一导电类型。该方法还包括在第一衬底区域的至少一部分和第二衬底区域的至少一部分上形成电介质层。该方法还包括在覆盖第一衬底区域的介电层的至少一部分上形成含金属的栅极层。该方法还包括通过含金属的栅极层将掺杂剂引入到第一衬底区域的至少一部分中。

4. 发明授权

US07297588B2 Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same 有权
标题翻译：电子器件包括含有含有一种或多种杂质的含金属层的栅电极及其形成方法
公开(公告)号：US07297588B2
公开(公告)日：2007-11-20
申请号：US11046079
申请日：2005-01-28
申请人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
发明人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
摘要翻译：可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数与没有含硼物质的含金属栅电极相比。

5. 发明授权

US06717226B2 Transistor with layered high-K gate dielectric and method therefor 有权
标题翻译：具有层状高K栅极电介质的晶体管及其方法
公开(公告)号：US06717226B2
公开(公告)日：2004-04-06
申请号：US10098706
申请日：2002-03-15
申请人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
发明人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.
摘要翻译：晶体管器件具有至少两层的栅极电介质，其中一个是氧化铪，另一个是不同于氧化铪的金属氧化物。氧化铪和金属氧化物也具有高介电常数。金属氧化物提供与氧化铪的界面，其作为污染物渗透的屏障。特别值得注意的是硼从多晶硅栅极渗透到氧化铪到半导体衬底。氧化铪在其结晶结构中通常具有晶界，其提供硼原子的路径。金属氧化物具有与氧化铪不同的结构，使得氧化铪中的硼的路径被金属氧化物阻挡。因此，提供高介电常数，同时防止硼从栅电极渗透到基板。

6. 发明申请

US20080001202A1 A METHOD OF MAKING METAL GATE TRANSISTORS 失效
标题翻译：制造金属栅极晶体管的方法
公开(公告)号：US20080001202A1
公开(公告)日：2008-01-03
申请号：US11427980
申请日：2006-06-30
申请人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
发明人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
IPC分类号： H01L29/94
CPC分类号： H01L27/1203 , H01L21/28105 , H01L21/823842 , H01L21/84 , H01L29/4966 , H01L29/517
摘要： A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.
摘要翻译：半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。第一层基本上是无氧的。响应于随后的热处理，功函数被第二导电层调制到期望的功函数。第二层是导电含氧金属。具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。金属的第三层沉积在第二层上。多晶硅层沉积在第三层上。第三层防止多晶硅层和含氧层一起反应。

7. 发明授权

US07655550B2 Method of making metal gate transistors 失效
标题翻译：制造金属栅晶体管的方法
公开(公告)号：US07655550B2
公开(公告)日：2010-02-02
申请号：US11427980
申请日：2006-06-30
申请人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
发明人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
IPC分类号： H01L21/4763
CPC分类号： H01L27/1203 , H01L21/28105 , H01L21/823842 , H01L21/84 , H01L29/4966 , H01L29/517
摘要： A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.
摘要翻译：半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。第一层基本上是无氧的。响应于随后的热处理，功函数被第二导电层调制到期望的功函数。第二层是导电含氧金属。具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。金属的第三层沉积在第二层上。多晶硅层沉积在第三层上。第三层防止多晶硅层和含氧层一起反应。

8. 发明授权

US06255204B1 Method for forming a semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US06255204B1
公开(公告)日：2001-07-03
申请号：US09316012
申请日：1999-05-21
申请人： Philip J. Tobin , Olubunmi O. Adetutu , Rama I. Hegde , Bikas Maiti
发明人： Philip J. Tobin , Olubunmi O. Adetutu , Rama I. Hegde , Bikas Maiti
IPC分类号： H01L214763
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/6656 , H01L29/7842
摘要： A first metal-containing material (22) is formed over a semiconductor device substrate (10). A second metal-containing material (32) is formed over the first metal containing material (22). The combination of the second metal-containing material (32) formed over the first metal-containing material (22) forms a metal stack (34). The metal stack (34) is annealed and a post-anneal stress of the metal stack (34) is less than an individual post-anneal stress of either one of the first conductive film (22) or the second conductive film (32).
摘要翻译：第一含金属材料（22）形成在半导体器件衬底（10）上。在第一含金属材料（22）之上形成第二含金属材料（32）。形成在第一含金属材料（22）上方的第二含金属材料（32）的组合形成金属叠层（34）。金属叠层（34）退火，并且金属叠层（34）的退火后应力小于第一导电膜（22）或第二导电膜（32）中的任一个的单个后退火应力。

9. 发明授权

US07091568B2 Electronic device including dielectric layer, and a process for forming the electronic device 有权
标题翻译：包括电介质层的电子器件，以及用于形成电子器件的工艺
公开(公告)号：US07091568B2
公开(公告)日：2006-08-15
申请号：US11023014
申请日：2004-12-22
申请人： Rama I. Hegde , Alexander A. Demkov , Philip J. Tobin , Dina H. Triyoso
发明人： Rama I. Hegde , Alexander A. Demkov , Philip J. Tobin , Dina H. Triyoso
IPC分类号： H01L29/76 , H01L21/8242
CPC分类号： H01L29/517 , C23C16/45529 , C23C16/45531 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/28185 , H01L21/28194 , H01L21/28229 , H01L21/3141 , H01L21/31641 , H01L21/31645 , H01L21/823842 , H01L29/4966
摘要： A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO2)(1-x)(ZrO2)x, wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.
摘要翻译：材料的混合物可以在电子器件的层内使用，以改善该层的电学和物理性质。在一组实施例中，该层可以是介电层，例如栅极介电层或电容器电介质层。电介质层可以包括O和两个或多个不同的金属元素。在一个具体实施方式中，两个不同的元件可以具有相同的单一氧化状态并且彼此可混溶。在一个实施例中，电介质层可以包括（HfO 2 2）（1-x）（ZrO 2 2）x 其中x在0和1之间.Hf和Zr中的每一个具有+4的单一氧化态。其他组合是可能的。改善的电学和物理性质可以包括更好地控制晶粒尺寸，晶粒尺寸分布，跨越衬底的层的厚度，改进的载流子迁移率，阈值电压稳定性或其任何组合。

10. 发明授权

US06972224B2 Method for fabricating dual-metal gate device 有权
公开(公告)号：US06972224B2
公开(公告)日：2005-12-06
申请号：US10400896
申请日：2003-03-27
申请人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
发明人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

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