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1. 发明申请

US20080001202A1 A METHOD OF MAKING METAL GATE TRANSISTORS 失效
标题翻译：制造金属栅极晶体管的方法
公开(公告)号：US20080001202A1
公开(公告)日：2008-01-03
申请号：US11427980
申请日：2006-06-30
申请人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
发明人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
IPC分类号： H01L29/94
CPC分类号： H01L27/1203 , H01L21/28105 , H01L21/823842 , H01L21/84 , H01L29/4966 , H01L29/517
摘要： A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.
摘要翻译：半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。第一层基本上是无氧的。响应于随后的热处理，功函数被第二导电层调制到期望的功函数。第二层是导电含氧金属。具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。金属的第三层沉积在第二层上。多晶硅层沉积在第三层上。第三层防止多晶硅层和含氧层一起反应。

2. 发明授权

US07655550B2 Method of making metal gate transistors 失效
标题翻译：制造金属栅晶体管的方法
公开(公告)号：US07655550B2
公开(公告)日：2010-02-02
申请号：US11427980
申请日：2006-06-30
申请人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
发明人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
IPC分类号： H01L21/4763
CPC分类号： H01L27/1203 , H01L21/28105 , H01L21/823842 , H01L21/84 , H01L29/4966 , H01L29/517
摘要： A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.
摘要翻译：半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。第一层基本上是无氧的。响应于随后的热处理，功函数被第二导电层调制到期望的功函数。第二层是导电含氧金属。具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。金属的第三层沉积在第二层上。多晶硅层沉积在第三层上。第三层防止多晶硅层和含氧层一起反应。

3. 发明授权

US07683439B2 Semiconductor device having a metal carbide gate with an electropositive element and a method of making the same 有权
标题翻译：具有具有正电性单元的金属碳化物栅极的半导体器件及其制造方法
公开(公告)号：US07683439B2
公开(公告)日：2010-03-23
申请号：US11685027
申请日：2007-03-12
申请人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
发明人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
IPC分类号： H01L27/088
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/4908 , H01L29/4958
摘要： A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.
摘要翻译：半导体器件结构形成在半导体衬底之上并且在半导体衬底上方具有栅极电介质，并且在栅极电介质上方具有栅极。在与栅极电介质的界面处的栅极包含过渡金属，碳和正电性元素。过渡金属由钽，钛，铪，锆，钼和钨组成。正电荷元素包括由IIA族元素，IIIB族元素和镧系元素组成的组中的一种。

4. 发明申请

US20080224185A1 SEMICONDUCTOR DEVICE HAVING A METAL CARBIDE GATE WITH AN ELECTROPOSITIVE ELEMENT AND A METHOD OF MAKING THE SAME 有权
标题翻译：具有电镀元件的金属碳化硅栅的半导体器件及其制造方法
公开(公告)号：US20080224185A1
公开(公告)日：2008-09-18
申请号：US11685027
申请日：2007-03-12
申请人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
发明人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/4908 , H01L29/4958
摘要： A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.
摘要翻译：半导体器件结构形成在半导体衬底之上并且在半导体衬底上方具有栅极电介质，并且在栅极电介质上方具有栅极。在与栅极电介质的界面处的栅极包含过渡金属，碳和正电性元素。过渡金属由钽，钛，铪，锆，钼和钨组成。正电荷元素包括由IIA族元素，IIIB族元素和镧系元素组成的组中的一种。

5. 发明授权

US06972224B2 Method for fabricating dual-metal gate device 有权
公开(公告)号：US06972224B2
公开(公告)日：2005-12-06
申请号：US10400896
申请日：2003-03-27
申请人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
发明人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

6. 发明授权

US08178401B2 Method for fabricating dual-metal gate device 有权
标题翻译：双金属栅极器件制造方法
公开(公告)号：US08178401B2
公开(公告)日：2012-05-15
申请号：US11530058
申请日：2006-09-08
申请人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
发明人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译：一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。诸如HfO 2的栅极电介质（34）沉积在半导体衬底上。牺牲层（35）接着沉积在栅极电介质上。牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是受牺牲层保护。第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

7. 发明申请

US20090286387A1 Modulation of Tantalum-Based Electrode Workfunction 审中-公开
标题翻译：钽电极工作功能的调制
公开(公告)号：US20090286387A1
公开(公告)日：2009-11-19
申请号：US12122178
申请日：2008-05-16
申请人： David C. Gilmer , Srikanth B. Samavedam , James K. Schaeffer , Voon-Yew Thean
发明人： David C. Gilmer , Srikanth B. Samavedam , James K. Schaeffer , Voon-Yew Thean
IPC分类号： H01L21/28 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4975
摘要： A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (14) over a gate dielectric layer (12) and then selectively introducing nitrogen into the portions of the first conductive layer (14) in the PMOS device region (1), either by annealing (42) a nitrogen-containing diffusion layer (22) formed in the PMOS device region (1) or by performing an ammonia anneal process (82) while the NMOS device region (2) is masked. By introducing nitrogen into the first conductive layer (14), the work function is modulated toward PMOS band edge.
摘要翻译：一种半导体工艺和装置，通过在栅介质层（12）上形成第一导电层（14）制造金属栅电极，然后选择性地将氮引入PMOS器件区域（1）中的第一导电层（14）的部分），通过在形成于PMOS器件区域（1）中的含氮扩散层（22）退火（42），或者在NMOS器件区域（2）被掩蔽的同时执行氨退火工艺（82）。通过将氮引入到第一导电层（14）中，功函数被调制到PMOS带边缘。

8. 发明授权

US07015153B1 Method for forming a layer using a purging gas in a semiconductor process 失效
标题翻译：在半导体工艺中使用吹扫气体形成层的方法
公开(公告)号：US07015153B1
公开(公告)日：2006-03-21
申请号：US10969634
申请日：2004-10-20
申请人： Dina H. Triyoso , Olubunmi O. Adetutu , David C. Gilmer , Darrell Roan , James K. Schaeffer , Philip J. Tobin , Hsing H. Tseng
发明人： Dina H. Triyoso , Olubunmi O. Adetutu , David C. Gilmer , Darrell Roan , James K. Schaeffer , Philip J. Tobin , Hsing H. Tseng
IPC分类号： H01L21/31
CPC分类号： C23C14/0057 , C23C16/30 , C23C16/45527 , H01L21/28229 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.
摘要翻译：一种用于形成半导体器件的至少一部分的方法包括提供半导体衬底，使第一前体气体流过衬底以形成覆盖半导体衬底的第一含金属层，并且在完成所述第一前体气体流动步骤使第一含氘吹扫气体流过第一含金属层，将氘掺入第一含金属层并且还吹扫第一前体气体。该方法还可以包括使第二前体气体流过第一含金属层以与第一含金属层反应以形成含金属化合物的层，并将第二含氘的净化气体流过含金属化合物的层层将氘并入含金属化合物的层中并且还吹扫第二前体气体。

9. 发明授权

US06717226B2 Transistor with layered high-K gate dielectric and method therefor 有权
标题翻译：具有层状高K栅极电介质的晶体管及其方法
公开(公告)号：US06717226B2
公开(公告)日：2004-04-06
申请号：US10098706
申请日：2002-03-15
申请人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
发明人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.
摘要翻译：晶体管器件具有至少两层的栅极电介质，其中一个是氧化铪，另一个是不同于氧化铪的金属氧化物。氧化铪和金属氧化物也具有高介电常数。金属氧化物提供与氧化铪的界面，其作为污染物渗透的屏障。特别值得注意的是硼从多晶硅栅极渗透到氧化铪到半导体衬底。氧化铪在其结晶结构中通常具有晶界，其提供硼原子的路径。金属氧化物具有与氧化铪不同的结构，使得氧化铪中的硼的路径被金属氧化物阻挡。因此，提供高介电常数，同时防止硼从栅电极渗透到基板。

10. 发明授权

US07868389B2 Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities 有权
标题翻译：电子器件包括含有含有一种或多种杂质的含金属层的栅电极
公开(公告)号：US07868389B2
公开(公告)日：2011-01-11
申请号：US11928314
申请日：2007-10-30
申请人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
发明人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823842
摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
摘要翻译：可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数与没有含硼物质的含金属栅电极相比。

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