专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07015153B1 Method for forming a layer using a purging gas in a semiconductor process 失效
标题翻译：在半导体工艺中使用吹扫气体形成层的方法
公开(公告)号：US07015153B1
公开(公告)日：2006-03-21
申请号：US10969634
申请日：2004-10-20
申请人： Dina H. Triyoso , Olubunmi O. Adetutu , David C. Gilmer , Darrell Roan , James K. Schaeffer , Philip J. Tobin , Hsing H. Tseng
发明人： Dina H. Triyoso , Olubunmi O. Adetutu , David C. Gilmer , Darrell Roan , James K. Schaeffer , Philip J. Tobin , Hsing H. Tseng
IPC分类号： H01L21/31
CPC分类号： C23C14/0057 , C23C16/30 , C23C16/45527 , H01L21/28229 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.
摘要翻译：一种用于形成半导体器件的至少一部分的方法包括提供半导体衬底，使第一前体气体流过衬底以形成覆盖半导体衬底的第一含金属层，并且在完成所述第一前体气体流动步骤使第一含氘吹扫气体流过第一含金属层，将氘掺入第一含金属层并且还吹扫第一前体气体。该方法还可以包括使第二前体气体流过第一含金属层以与第一含金属层反应以形成含金属化合物的层，并将第二含氘的净化气体流过含金属化合物的层层将氘并入含金属化合物的层中并且还吹扫第二前体气体。

2. 发明授权

US07704821B2 In-situ nitridation of high-k dielectrics 有权
标题翻译：高k电介质的原位氮化
公开(公告)号：US07704821B2
公开(公告)日：2010-04-27
申请号：US11146826
申请日：2005-06-07
申请人： Dina H. Triyoso , Olubunmi O. Adetutu , Hsing H. Tseng
发明人： Dina H. Triyoso , Olubunmi O. Adetutu , Hsing H. Tseng
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack includes depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers includes performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers includes depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer includes pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.
摘要翻译：用于形成栅极电介质的半导体制造工艺包括沉积高k电介质堆叠，其包括将氮掺杂到原位的高k电介质堆叠中。形成覆盖在电介质堆叠上的顶部高k电介质，并且电介质堆叠和顶部电介质被退火。沉积介电堆叠包括沉积多个高k电介质层，其中每个层以不同的处理步骤或一组步骤形成。沉积一个电介质层包括执行多个原子层沉积工艺以形成多个高k子层，其中每个子层是单层膜。沉积多个子层包括沉积无氮的子层并沉积含氮的子层。沉积无氮子层包括用HfCl 4脉冲ALD室，用惰性气体冲洗室，用H 2 O或D 2 O脉冲室，并用惰性气体清洗室。

3. 发明授权

US06717226B2 Transistor with layered high-K gate dielectric and method therefor 有权
标题翻译：具有层状高K栅极电介质的晶体管及其方法
公开(公告)号：US06717226B2
公开(公告)日：2004-04-06
申请号：US10098706
申请日：2002-03-15
申请人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
发明人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.
摘要翻译：晶体管器件具有至少两层的栅极电介质，其中一个是氧化铪，另一个是不同于氧化铪的金属氧化物。氧化铪和金属氧化物也具有高介电常数。金属氧化物提供与氧化铪的界面，其作为污染物渗透的屏障。特别值得注意的是硼从多晶硅栅极渗透到氧化铪到半导体衬底。氧化铪在其结晶结构中通常具有晶界，其提供硼原子的路径。金属氧化物具有与氧化铪不同的结构，使得氧化铪中的硼的路径被金属氧化物阻挡。因此，提供高介电常数，同时防止硼从栅电极渗透到基板。

4. 发明授权

US06902969B2 Process for forming dual metal gate structures 有权
标题翻译：双金属门结构形成工艺
公开(公告)号：US06902969B2
公开(公告)日：2005-06-07
申请号：US10632473
申请日：2003-07-31
申请人： Olubunmi O. Adetutu , Hsing H. Tseng , Wei E. Wu
发明人： Olubunmi O. Adetutu , Hsing H. Tseng , Wei E. Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.
摘要翻译：半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质/蚀刻停止层堆叠直接接触的第二金属类型的N沟道栅极堆叠。通过干蚀刻蚀刻N沟道栅极堆叠和P沟道栅极堆叠。栅极电介质或蚀刻停止件可以与衬底接触。蚀刻停止层防止第一和第二金属层的干蚀刻蚀刻通过栅极电介质并且刨削下面的衬底。

5. 发明授权

US06686282B1 Plated metal transistor gate and method of formation 有权
标题翻译：镀金属晶体管栅极和形成方法
公开(公告)号：US06686282B1
公开(公告)日：2004-02-03
申请号：US10403967
申请日：2003-03-31
申请人： Cindy Simpson , Hsing H. Tseng , Olubunmi O. Adetutu
发明人： Cindy Simpson , Hsing H. Tseng , Olubunmi O. Adetutu
IPC分类号： H01L2144
CPC分类号： H01L21/823842 , H01L21/28079
摘要： Using plating, metal gates for N channel and P channel transistors are formed of different materials to achieve the appropriate work function for these N and P channel transistors. The plating is achieved with a seed layer consistent with the growth of the desired layer. The preferred materials are selected from the platinum metals, which comprise ruthenium, ruthenium oxide, iridium, palladium, platinum, nickel, osmium, and cobalt. These are attractive metals because they are relatively high conductivity, can be plated, and provide a good choice of work functions for forming P and N channel transistors.
摘要翻译：使用电镀，N沟道和P沟道晶体管的金属栅极由不同的材料形成，以实现这些N和P沟道晶体管的适当的功函数。用与期望层的生长一致的种子层实现电镀。优选的材料选自包含钌，氧化钌，铱，钯，铂，镍，锇和钴的铂金属。这些是有吸引力的金属，因为它们具有相对高的导电性，可以被电镀，并且提供了用于形成P和N沟道晶体管的工作功能的良好选择。

6. 发明授权

US07402472B2 Method of making a nitrided gate dielectric 失效
标题翻译：制造氮化栅极电介质的方法
公开(公告)号：US07402472B2
公开(公告)日：2008-07-22
申请号：US11067257
申请日：2005-02-25
申请人： Sangwoo Lim , Paul A. Grudowski , Tien Ying Luo , Olubunmi O. Adetutu , Hsing H. Tseng
发明人： Sangwoo Lim , Paul A. Grudowski , Tien Ying Luo , Olubunmi O. Adetutu , Hsing H. Tseng
IPC分类号： H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译：用氮化步骤和退火处理栅极电介质。之后，进行另外的氮化步骤和退火。第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。

7. 发明授权

US07235502B2 Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors 有权
标题翻译：过渡介电层提高高介电常数晶体管的可靠性和性能
公开(公告)号：US07235502B2
公开(公告)日：2007-06-26
申请号：US11096515
申请日：2005-03-31
申请人： Sriram S. Kalpat , Voon-Yew Thean , Hsing H. Tseng , Olubunmi O. Adetutu
发明人： Sriram S. Kalpat , Voon-Yew Thean , Hsing H. Tseng , Olubunmi O. Adetutu
IPC分类号： H01L21/31
CPC分类号： H01L21/022 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L29/513 , H01L29/517
摘要： A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon. Forming the transitional dielectric layer (205) may include performing multiple cycles of an atomic layer deposition process (500) where a precursor concentration for each cycle differs from the precursor concentration of the preceding cycle.
摘要翻译：栅极电介质结构（201）制造工艺包括形成覆盖氧化硅膜（204）的过渡电介质膜（205）。然后形成覆盖在过渡介电膜（205）的上表面上的高介电常数膜（206）。氧化硅膜（204）界面处的过渡电介质膜（205）的组成主要包括硅和氧。高K电介质（206）和上表面附近的过渡电介质膜（205）的组成主要包括金属元素和氧。形成过渡电介质膜（205）可以包括形成多个过渡介电层（207），其中每个连续的过渡介电层（207）的组成具有较高的金属元素浓度和较低的硅浓度。形成过渡电介质层（205）可以包括执行原子层沉积工艺（500）的多个循环，其中每个循环的前体浓度与先前循环的前体浓度不同。

8. 发明授权

US07144825B2 Multi-layer dielectric containing diffusion barrier material 有权
标题翻译：多层电介质含有扩散阻挡材料
公开(公告)号：US07144825B2
公开(公告)日：2006-12-05
申请号：US10687271
申请日：2003-10-16
申请人： Olubunmi O. Adetutu , Tien Ying Luo , Hsing H. Tseng
发明人： Olubunmi O. Adetutu , Tien Ying Luo , Hsing H. Tseng
IPC分类号： H01L21/00
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/518
摘要： A method for forming a dielectric is disclosed. The method comprises forming a first dielectric layer over semiconductor material. A diffusion barrier material is introduced into the first dielectric layer. Lastly, a second dielectric layer is formed over the first dielectric layer after the introducing.
摘要翻译：公开了形成电介质的方法。该方法包括在半导体材料上形成第一介电层。扩散阻挡材料被引入到第一介电层中。最后，在引入之后，在第一电介质层上形成第二电介质层。

9. 发明授权

US06884685B2 Radical oxidation and/or nitridation during metal oxide layer deposition process 有权
标题翻译：金属氧化物层沉积过程中的自由基氧化和/或氮化
公开(公告)号：US06884685B2
公开(公告)日：2005-04-26
申请号：US10366777
申请日：2003-02-14
申请人： Tien Ying Luo , Ricardo Garcia , Hsing H. Tseng
发明人： Tien Ying Luo , Ricardo Garcia , Hsing H. Tseng
IPC分类号： C23C16/30 , C23C16/40 , H01L21/28 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28185 , C23C16/308 , C23C16/40 , H01L21/02181 , H01L21/02271 , H01L21/02362 , H01L21/28194 , H01L21/28202 , H01L21/3141 , H01L21/3143 , H01L21/31604 , H01L21/3162 , H01L21/31645 , H01L29/517 , H01L29/518
摘要： A metal oxide high-k dielectric is deposited on a semiconductor wafer in a manner that reduces dangling bonds in the dielectric without significantly thickening interfacial oxide thickness. A metal oxide precursor and radical oxygen and/or radical nitrogen are co-flowed over the semiconductor wafer to form the high-k dielectric. The radicals bond to dangling bonds of the metal of the metal oxide during the deposition process that is performed at the regular deposition temperature of less than about 400 degrees Celsius. The radical oxygen and radical nitrogen do not require the higher temperatures generally required in an anneal in order to attach to the dangling bonds of the metal. Thus, a high temperature post deposition anneal, which tends to cause interfacial oxide growth, is not required. The dielectric is of higher quality than is typical because the dangling bonds are removed during deposition rather than after the dielectric has been deposited.
摘要翻译：金属氧化物高k电介质沉积在半导体晶片上，以减少电介质中的悬挂键而不显着增加界面氧化物厚度。金属氧化物前体和自由基氧和/或自由基氮共同流过半导体晶片以形成高k电介质。在沉积过程中，基团键合到金属氧化物的金属的悬挂键，其在小于约400摄氏度的常规沉积温度下进行。自由基氧和自由基氮不需要在退火中通常需要的较高温度以附着到金属的悬挂键上。因此，不需要倾向于引起界面氧化物生长的高温后沉积退火。电介质的质量比典型值高，因为在沉积期间移除悬挂键，而不是沉积电介质后。

10. 发明授权

US07214590B2 Method of forming an electronic device 有权
标题翻译：电子设备的形成方法
公开(公告)号：US07214590B2
公开(公告)日：2007-05-08
申请号：US11098874
申请日：2005-04-05
申请人： Sangwoo Lim , Paul A. Grudowski , Mohamad M. Jahanbani , Hsing H. Tseng , Choh-Fei Yeap
发明人： Sangwoo Lim , Paul A. Grudowski , Mohamad M. Jahanbani , Hsing H. Tseng , Choh-Fei Yeap
IPC分类号： H01L21/336
CPC分类号： H01L21/823462
摘要： A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.
摘要翻译：形成电子器件的方法包括蚀刻第一栅极介电层的一部分以减小该部分内的栅极介电层的厚度。在一个实施例中，未被蚀刻的部分可以被掩模覆盖。在另一个实施例中，不同部分可以在不同时间被蚀刻，以给予第一栅极介电层不同的厚度。在特定实施例中，可以在蚀刻该部分之后在第一栅极电介质层上形成第二栅极电介质层。第二栅极介电层可以具有大于第一栅极介电层的介电常数的介电常数。可以进行随后的栅电极和源/漏区形成以形成晶体管结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式