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1. 发明授权

US06982902B2 MRAM array having a segmented bit line 失效
标题翻译： MRAM阵列具有分段位线
公开(公告)号：US06982902B2
公开(公告)日：2006-01-03
申请号：US10679160
申请日：2003-10-03
申请人： Dietmar Gogl , John K. DeBrosse
发明人： Dietmar Gogl , John K. DeBrosse
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C11/15
摘要： A magneto-resistive random access memory (MRAM) array comprises global bit lines segmented using a plurality of local bit lines. A read/write controller is connected to the switches. Switches couple the global bit line to the local bit lines. The MRAM array has low leakage currents and facilitates a high signal-to-noise (S/N) ratio of read and write operations.
摘要翻译：磁阻随机存取存储器（MRAM）阵列包括使用多个局部位线分割的全局位线。读/写控制器连接到交换机。开关将全局位线耦合到局部位线。 MRAM阵列具有低漏电流，并有助于读写操作的高信噪比（S / N）。

2. 发明授权

US07239537B2 Method and apparatus for current sense amplifier calibration in MRAM devices 有权
标题翻译：用于MRAM器件中电流检测放大器校准的方法和装置
公开(公告)号：US07239537B2
公开(公告)日：2007-07-03
申请号：US10905585
申请日：2005-01-12
申请人： John K. DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
发明人： John K. DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.
摘要翻译：校准磁性随机存取存储器（MRAM）电流检测放大器包括与第一负载装置并联的第一多个调整晶体管，第一负载装置与读出放大器的数据侧相关联。与第二负载装置并联地选择性地配置第二组微调晶体管，第二负载装置与感测放大器的参考侧相关联。单独激活第一和第二多个微调晶体管，以补偿相对于读出放大器的数据和参考侧的器件失配。

3. 发明申请

US20080310210A1 Semiconductor memory device and method of operation 审中-公开
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20080310210A1
公开(公告)日：2008-12-18
申请号：US11818196
申请日：2007-06-13
申请人： Dietmar Gogl , Ulrich Klostermann
发明人： Dietmar Gogl , Ulrich Klostermann
IPC分类号： G11C7/02
CPC分类号： G11C13/0011 , G11C8/08 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/79
摘要： A memory cell is disclosed. The memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between the first terminal and the second terminal. The first terminal of the select transistor is coupled to the second terminal of the storage element. A bit line is coupled to the first terminal of the storage element, a first word line is coupled to the control terminal of the select transistor, and a second word line is coupled to the second terminal of the select transistor.
摘要翻译：公开了一种存储器单元。存储单元包括存储元件，其包括第一端子和第二端子，以及选择晶体管，其包括第一端子，第二端子和控制端子。选择晶体管的控制端子处的电压影响在第一端子和第二端子之间流动的电流。选择晶体管的第一端子耦合到存储元件的第二端子。位线耦合到存储元件的第一端子，第一字线耦合到选择晶体管的控制端子，第二字线耦合到选择晶体管的第二端子。

4. 发明授权

US07433253B2 Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module 有权
标题翻译：集成电路，集成电路的操作方法，集成电路的制造方法，存储器模块，可堆叠存储器模块
公开(公告)号：US07433253B2
公开(公告)日：2008-10-07
申请号：US11768508
申请日：2007-06-26
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02 , G11C11/00
CPC分类号： G11C7/067 , G11C5/02 , G11C5/04 , G11C11/1673 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C2013/0054 , G11C2207/063 , G11C2213/71 , G11C2213/79
摘要： An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.
摘要翻译：集成电路具有电流检测放大器，其包括具有第一输入，第二输入和输出的电压比较器; 耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置，耦合在电压比较器的第二输入端和第二输入信号节点之间的第二钳位装置，具有第一侧和第二电流镜第一侧包括耦合在电压源和第一钳位装置之间的第一晶体管和电流镜第二侧，其包括耦合在电压源和第二钳位装置之间的第二晶体管，以及感测方案，包括主动平衡耦合到第二晶体管的源极和漏极的电容。

5. 发明申请

US20070121391A1 Magnetoresistive random access memory array 有权
标题翻译：磁阻随机存取存储器阵列
公开(公告)号：US20070121391A1
公开(公告)日：2007-05-31
申请号：US11288494
申请日：2005-11-29
申请人： Dietmar Gogl , Daniel Braun
发明人： Dietmar Gogl , Daniel Braun
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C8/10
摘要： A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A switching circuit is configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.
摘要翻译：公开了磁存储器。在一个实施例中，磁存储阵列包括多个单元列和一对参考单元列，包括第一参考单元列和第二参考单元列。比较器具有第一和第二输入端。开关电路被配置为将每个单元列连接到与第二输入端并联耦合的第一输入端和一对参考单元列，并且被配置为将第一参考单元列连接到第一输入端，而第二参考单元列参考单元格列到第二个输入端。

6. 发明授权

US07200033B2 MRAM with coil for creating offset field 有权
标题翻译：带有线圈的MRAM用于创建偏移场
公开(公告)号：US07200033B2
公开(公告)日：2007-04-03
申请号：US10998808
申请日：2004-11-30
申请人： Daniel Braun , Dietmar Gogl
发明人： Daniel Braun , Dietmar Gogl
IPC分类号： G11C11/00 , G11C5/06 , G11C11/14 , G11C11/15 , G11C7/02
CPC分类号： H01L27/222 , G11C11/16
摘要： An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers that are antiferromagnetically coupled, wherein a coil surrounds the memory chip for creating a magnetic offset field. Further, a method of writing to an MRAM chip includes bringing the memory cells into an active state exhibiting a reduced switching field before writing thereto and bringing the memory cells into a passive state exhibiting enlarged switching field after writing thereto.
摘要翻译： MRAM存储器芯片包括多个磁阻存储单元，每个磁阻存储单元包括具有第一（固定）和第二（自由）磁区的磁性隧道结，其中第二磁区包括反铁磁耦合的至少两个铁磁层，其中线圈围绕用于产生磁偏移场的存储芯片。此外，写入MRAM芯片的方法包括在写入之前使存储单元进入呈现减小的开关场的有效状态，并且在写入之后使存储单元成为展现放大开关场的被动状态。

7. 发明申请

US20060104136A1 Sense amplifier bitline boost circuit 有权
标题翻译：感应放大器位线升压电路
公开(公告)号：US20060104136A1
公开(公告)日：2006-05-18
申请号：US10988787
申请日：2004-11-15
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02
CPC分类号： G11C5/145 , G11C7/06 , G11C7/12 , G11C11/16 , G11C2207/063
摘要： A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.
摘要翻译：包括钳位装置和电流镜的电流检测放大器被配置为使用位线升压电路感测MTJ存储器单元的电阻，以缩短寄生电路电容的充电时间。位线升压电路包括耦合到参考电压的源极跟随器和耦合到另一个电压源的开关。在感测存储单元的电阻的初始时段期间，该开关能够导通。位线升压电路中的源极跟随器被配置为将输入信号的电压钳位在与钳位装置基本相同的电平上，并提供额外的电流以缩短对寄生电容充电的周期。所得到的电流检测放大器可用于实现具有快速可靠的读取时间和低制造成本的存储器件。

8. 发明授权

US06807089B2 Method for operating an MRAM semiconductor memory configuration 失效
标题翻译：用于操作MRAM半导体存储器配置的方法
公开(公告)号：US06807089B2
公开(公告)日：2004-10-19
申请号：US10685082
申请日：2003-10-14
申请人： Dietmar Gogl , Till Schloesser
发明人： Dietmar Gogl , Till Schloesser
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： In a method for operating an MRAM semiconductor memory configuration, for the purpose of reading an item of stored information, reversible magnetic changes are made to the TMR cell and a current that is momentarily altered as a result is compared with the original read signal. As a result, the TMR memory cell itself can serve as a reference, even though the information in the TMR memory cell is not destroyed, i.e. writing-back does not have to be effected. The method can preferably be applied to an MRAM memory configuration in which a plurality of TMR cells are connected, in parallel, to a selection transistor and in which there is a write line which is not electrically connected to the memory cell.
摘要翻译：在用于操作MRAM半导体存储器配置的方法中，为了读取存储的信息的项目，对TMR单元进行可逆的磁性改变，并且将与暂时改变的电流作为结果与原始读取信号进行比较。结果，TMR存储单元本身可以用作参考，即使TMR存储单元中的信息不被破坏，即不需要进行回写。该方法可以优选地应用于其中多个TMR单元并联连接到选择晶体管并且其中存在没有电连接到存储器单元的写入线的MRAM存储器配置。

9. 发明授权

US06483768B2 Current driver configuration for MRAM 有权
标题翻译： MRAM的当前驱动程序配置
公开(公告)号：US06483768B2
公开(公告)日：2002-11-19
申请号：US09898221
申请日：2001-07-03
申请人： Thomas Böhm , Dietmar Gogl , Gerhard Müller , Thomas Röhr
发明人： Thomas Böhm , Dietmar Gogl , Gerhard Müller , Thomas Röhr
IPC分类号： G11C800
CPC分类号： G11C11/16 , G11C7/12
摘要： A current driver configuration for MRAMs includes word-line drivers and bit-line drivers at respective first ends of word lines and bit lines. The word line drivers and the bit line drivers each include a series circuit formed by an n-channel field-effect transistor and a current source. Further series circuits are provided at the respective second ends of the word lines and the bit lines. Each of the further series circuits includes a second n-channel field-effect transistor and a voltage source.
摘要翻译： MRAM的当前驱动器配置包括在字线和位线的相应第一端处的字线驱动器和位线驱动器。字线驱动器和位线驱动器各自包括由n沟道场效应晶体管和电流源形成的串联电路。在字线和位线的各自的第二端设置有更多的串联电路。每个其它串联电路包括第二n沟道场效应晶体管和电压源。

10. 发明授权

US09135965B2 Memory controller and method for interleaving DRAM and MRAM accesses 有权
标题翻译：用于交错DRAM和MRAM访问的存储器控制器和方法
公开(公告)号：US09135965B2
公开(公告)日：2015-09-15
申请号：US13328867
申请日：2011-12-16
申请人： Syed M. Alam , Thomas Andre , Dietmar Gogl
发明人： Syed M. Alam , Thomas Andre , Dietmar Gogl
IPC分类号： G11C11/00 , G11C7/10 , G11C11/4076 , G11C8/04
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).
摘要翻译：描述了用于交错易失性和非易失性存储器的不同延迟和页面大小的存储器控制器和方法，其中单个DDR3存储器控制器与包括至少非易失性存储器的多个存储器模块进行通信，例如，自旋转矩磁性随机存取存储器集成在具有易失性存储器的不同等级或信道中，例如动态随机存取存储器（DRAM）。

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