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1. 发明授权

US08578222B2 SerDes power throttling as a function of detected error rate 有权
标题翻译： SerDes功率节流作为检测到的错误率的函数
公开(公告)号：US08578222B2
公开(公告)日：2013-11-05
申请号：US13029934
申请日：2011-02-17
申请人： Dexter T Chun , Jack K Wolf , Jungwon Suh , Tirdad Sowlati
发明人： Dexter T Chun , Jack K Wolf , Jungwon Suh , Tirdad Sowlati
IPC分类号： G06F11/00
CPC分类号： H04L12/12 , H04L1/0001 , H04L1/0036 , H04L25/02 , H04W52/0209 , Y02D70/00
摘要： A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.
摘要翻译：系统涉及从第一集成电路（IC）到第二IC的第一SerDes链路以及从第二IC到第一IC的第二链路。调整第一链路的电路中的功率消耗设置以控制功率消耗，使得第一链路的误码率保持在范围的下限基本上大于零的范围内。调整用于第二链路的电路中的功率消耗设置以控制功率消耗，使得第二链路的误码率保持在范围内，其范围的下限基本上大于零。在一个示例中，第二IC中的电路检测第一链路中的错误并通过第二链路报告。第一个IC使用报告的信息来确定第一个链路的误码率。

2. 发明申请

US20120216084A1 SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE 有权
标题翻译：作为检测到的错误率的功能将功率节制作为电源
公开(公告)号：US20120216084A1
公开(公告)日：2012-08-23
申请号：US13029934
申请日：2011-02-17
申请人： Dexter T. Chun , Jack K. Wolf , Jungwon Suh , Tirdad Sowlati
发明人： Dexter T. Chun , Jack K. Wolf , Jungwon Suh , Tirdad Sowlati
IPC分类号： G06F11/00
CPC分类号： H04L12/12 , H04L1/0001 , H04L1/0036 , H04L25/02 , H04W52/0209 , Y02D70/00
摘要： A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.
摘要翻译：系统涉及从第一集成电路（IC）到第二IC的第一SerDes链路以及从第二IC到第一IC的第二链路。调整第一链路的电路中的功率消耗设置以控制功率消耗，使得第一链路的误码率保持在范围的下限基本上大于零的范围内。调整用于第二链路的电路中的功率消耗设置以控制功率消耗，使得第二链路的误码率保持在范围内，其范围的下限基本上大于零。在一个示例中，第二IC中的电路检测第一链路中的错误并通过第二链路报告。第一个IC使用报告的信息来确定第一个链路的误码率。

3. 发明授权

US08839020B2 Dual mode clock/data recovery circuit 有权
标题翻译：双模时钟/数据恢复电路
公开(公告)号：US08839020B2
公开(公告)日：2014-09-16
申请号：US13420800
申请日：2012-03-15
申请人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
发明人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
IPC分类号： G06F1/04 , G06F1/12 , H03L7/00 , H04B7/212 , H04L12/28 , H04J3/06 , H04L7/00 , H04B1/16 , G06F15/16
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

4. 发明授权

US08570077B2 Methods and implementation of low-power power-on control circuits 有权
标题翻译：低功率上电控制电路的方法与实现
公开(公告)号：US08570077B2
公开(公告)日：2013-10-29
申请号：US12971527
申请日：2010-12-17
申请人： Chang Ki Kwon , Craig E. Borden , Steve J. Halter , Tirdad Sowlati
发明人： Chang Ki Kwon , Craig E. Borden , Steve J. Halter , Tirdad Sowlati
IPC分类号： H03L7/00
CPC分类号： H03K17/22 , G01R19/2503 , G06F1/26 , G06F1/32
摘要： Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply.
摘要翻译：公开了低功率上电控制电路的方法和实现。在特定实施例中，一种装置包括由第一电压源供电的功率检测器电路。至少一个电压电平移位装置耦合到第二电压源，并且将测试输入提供给功率检测器电路。可选的泄漏自控装置可以减少与第一电源和第二电源相关联的不想要的泄漏电流。

5. 发明授权

US07706760B2 System and method for saturation detection, correction and recovery in a polar transmitter 有权
标题翻译：用于极性发射机饱和检测，校正和恢复的系统和方法
公开(公告)号：US07706760B2
公开(公告)日：2010-04-27
申请号：US11431758
申请日：2006-05-10
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Darioush Agahi
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Darioush Agahi
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H04B1/0475 , H03F1/32 , H03F1/34 , H03F3/189 , H03F3/24 , H03F2200/438 , H03G3/3047 , H04B2001/0433
摘要： A system for saturation detection, correction and recovery in a power amplifier includes a power amplifier, a closed power control loop configured to develop a power control signal (VPC), and power control circuitry configured to reduce the power control signal if the power amplifier is operating in a saturation mode.
摘要翻译：一种用于功率放大器中的饱和度检测，校正和恢复的系统包括：功率放大器，被配置为开发功率控制信号（VPC）的闭合功率控制回路;以及功率控制电路，其被配置为如果功率放大器为在饱和模式下工作。

6. 发明授权

US07499682B2 Dual voltage regulator for a supply voltage controlled power amplifier in a closed power control loop 有权
标题翻译：双电压调节器，用于电源电压控制功率放大器，在闭合功率控制回路中
公开(公告)号：US07499682B2
公开(公告)日：2009-03-03
申请号：US11137197
申请日：2005-05-24
申请人： Dmitriy Rozenblit , Tirdad Sowlati
发明人： Dmitriy Rozenblit , Tirdad Sowlati
IPC分类号： H04B1/04
CPC分类号： H03F1/0233 , H03F1/02 , H03F1/0205 , H03F3/24 , H03F2200/207 , H03F2200/504 , H04B2001/045
摘要： A supply voltage controlled power amplifier that comprises a power amplifier, a closed power control feedback loop configured to generate a power control signal, and a dual voltage regulator coupled to the power control feedback loop, the dual voltage regulator comprising a first regulator stage and a second regulator stage, wherein the closed power control loop minimizes noise generated by the first regulator stage.
摘要翻译：一种电源电压控制功率放大器，包括功率放大器，被配置为产生功率控制信号的闭合功率控制反馈回路，以及耦合到功率控制反馈回路的双电压调节器，所述双电压调节器包括第一调节器级和第二调节器级，其中闭合功率控制回路最小化由第一调节器级产生的噪声。

7. 发明申请

US20070014381A1 Polar loop radio frequency (RF) transmitter having increased dynamic range amplitude control 有权
标题翻译：极地环射频（RF）发射机具有增加的动态范围幅度控制
公开(公告)号：US20070014381A1
公开(公告)日：2007-01-18
申请号：US11180940
申请日：2005-07-13
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Morten Damgaard
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Morten Damgaard
IPC分类号： H03D1/24 , H04L25/49 , H04L27/04
CPC分类号： H04L27/3809 , H03C1/00 , H03G3/3047 , H04L27/08 , H04L27/361 , H04W52/06 , H04W52/36
摘要： A closed loop power control system for a radio frequency (RF) transmitter comprises a first variable gain element located in a power control loop and configured to receive a power level signal and an inverse representation of a power control signal, a second variable gain element located in the power control loop and configured to receive an error signal and the power control signal, and a third variable gain element configured to receive an amplitude modulated (AM) signal and the power control signal, the third variable gain element having a gain characteristic configured to operate to reduce the gain applied to the AM signal when the power control signal falls below a minimum predetermined value, and to provide the AM signal as a reference signal.
摘要翻译：用于射频（RF）发射机的闭环功率控制系统包括位于功率控制环路中并被配置为接收功率电平信号和功率控制信号的反向表示的第一可变增益元件，位于在所述功率控制回路中并且被配置为接收误差信号和所述功率控制信号，以及第三可变增益元件，被配置为接收幅度调制（AM）信号和所述功率控制信号，所述第三可变增益元件具有构造的增益特性以在功率控制信号低于最小预定值时降低施加到AM信号的增益，并且提供AM信号作为参考信号。

8. 发明申请

US20050070233A1 ENVELOPE ERROR EXTRACTION IN IF/RF FEEDBACK LOOPS 失效
标题翻译： IF / RF反馈信号中的ENVELOPE ERROR EXTRACTION
公开(公告)号：US20050070233A1
公开(公告)日：2005-03-31
申请号：US10672903
申请日：2003-09-26
申请人： Tirdad Sowlati
发明人： Tirdad Sowlati
IPC分类号： H04B1/04 , H04Q7/32
CPC分类号： H04B1/0475
摘要： A system for detecting and extracting a signal envelope is disclosed. Embodiments of the invention provide for substantially linear operation and a low DC offset that is contributed generally by mismatch of a differential resistor.
摘要翻译：公开了一种用于检测和提取信号包络的系统。本发明的实施例提供基本上线性的操作和通常由差分电阻器的失配而有贡献的低DC偏移。

9. 发明授权

US06657425B2 Power measurement circuit including harmonic filter 有权
标题翻译：功率测量电路包括谐波滤波器
公开(公告)号：US06657425B2
公开(公告)日：2003-12-02
申请号：US09891668
申请日：2001-06-26
申请人： Tirdad Sowlati , Sifen Luo
发明人： Tirdad Sowlati , Sifen Luo
IPC分类号： G01R2502
CPC分类号： G01R21/12 , G01R21/10
摘要： A shorting element, preferably a resonant inductor-capacitor circuit, is inserted in parallel with a sense transistor, which itself is in parallel with a power transistor. The use of the shorting element in combination with the sense transistor, provides a technique to have a monotonic power detection. The shorting element eliminates extraneous currents caused by inherent collector-base and collector-substrate diodes of sense transistor, and also eliminates the extraneous collector voltage swing of the sense transistor caused by mutual coupling between inductors connected to the power and sense transistors.
摘要翻译：短路元件，优选谐振电感器 - 电容器电路与感测晶体管并联插入，读出晶体管本身与功率晶体管并联。使用短路元件与感测晶体管组合提供了一种具有单调功率检测的技术。短路元件消除了由感测晶体管的固有集电极 - 基极和集电极 - 基极二极管引起的外部电流，并且还消除了由连接到功率和感测晶体管的电感器之间的相互耦合引起的感测晶体管的外部集电极电压摆幅。

10. 发明授权

US06496074B1 Cascode bootstrapped analog power amplifier circuit 失效
标题翻译： Cascode自举模拟功率放大器电路
公开(公告)号：US06496074B1
公开(公告)日：2002-12-17
申请号：US09671890
申请日：2000-09-28
申请人： Tirdad Sowlati
发明人： Tirdad Sowlati
IPC分类号： H03F122
CPC分类号： H03F1/523 , H03F1/223
摘要： A cascode bootstrapped analog power amplifier circuit includes a first MOSFET and a second MOSFET connected in series and coupled between a dc voltage source terminal and a common terminal. An rf input signal terminal is coupled to a gate electrode of the first MOSFET and a dc control voltage terminal is coupled to a gate electrode of the second MOSFET, with a unidirectionally-conducting element such as a diode-connected MOSFET being coupled between a drain electrode and the gate electrode of the second MOSFET. The output of the amplifier circuit is taken from the drain electrode of the second MOSFET. This circuit configuration, permits he first and second MOSFETs to withstand a larger output voltage swing, thus permitting the use of a higher supply voltage and resulting in a substantially increased maximum output power capability for a given load value.
摘要翻译：级联自举模拟功率放大器电路包括串联连接并耦合在直流电压源端子和公共端子之间的第一MOSFET和第二MOSFET。 RF输入信号端子耦合到第一MOSFET的栅电极，并且直流控制电压端子耦合到第二MOSFET的栅电极，其中单向导电元件例如二极管连接的MOSFET耦合在漏极电极和第二MOSFET的栅电极。放大器电路的输出取自第二MOSFET的漏电极。该电路配置允许他的第一和第二MOSFET承受更大的输出电压摆幅，从而允许使用更高的电源电压，并且对于给定的负载值而导致基本上增加的最大输出功率能力。

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