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1. 发明申请

US20080151673A1 PG-Gated Data Retention Technique for Reducing Leakage in Memory Cells 失效
标题翻译：用于减少记忆细胞渗漏的PG门控数据保留技术
公开(公告)号：US20080151673A1
公开(公告)日：2008-06-26
申请号：US11615422
申请日：2006-12-22
申请人： Farzan Fallah , Behnam Amelifard , Massoud Pedram
发明人： Farzan Fallah , Behnam Amelifard , Massoud Pedram
IPC分类号： G11C5/14
CPC分类号： G11C11/417
摘要： A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept a ground. In one embodiment, the method includes forming the cell to accept selectively applied external voltages, wherein the external voltages are selected to minimize leakage current in the cell. In another embodiment, the method includes forming at least one of the first and the second transistors to have a channel width and/or a threshold voltage selected to minimize a total leakage current in the cell.
摘要翻译：形成存储单元的方法包括将存储单元的电源轨和可操作以接受电源电压的节点之间的第一晶体管耦合。该方法还包括将第二晶体管耦合在电池的接地导轨和可操作以接受接地的节点之间。在一个实施例中，该方法包括形成电池以接受选择性地施加的外部电压，其中选择外部电压以最小化电池中的泄漏电流。在另一个实施例中，该方法包括形成第一和第二晶体管中的至少一个以具有选择的沟道宽度和/或阈值电压以最小化单元中的总泄漏电流。

2. 发明授权

US08839020B2 Dual mode clock/data recovery circuit 有权
标题翻译：双模时钟/数据恢复电路
公开(公告)号：US08839020B2
公开(公告)日：2014-09-16
申请号：US13420800
申请日：2012-03-15
申请人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
发明人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
IPC分类号： G06F1/04 , G06F1/12 , H03L7/00 , H04B7/212 , H04L12/28 , H04J3/06 , H04L7/00 , H04B1/16 , G06F15/16
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

3. 发明授权

US07573775B2 Setting threshold voltages of cells in a memory block to reduce leakage in the memory block 失效
标题翻译：设置存储器块中的单元的阈值电压以减少存储器块中的泄漏
公开(公告)号：US07573775B2
公开(公告)日：2009-08-11
申请号：US11673245
申请日：2007-02-09
申请人： Farzan Fallah , Behnam Amelifard , Massoud Pedram
发明人： Farzan Fallah , Behnam Amelifard , Massoud Pedram
IPC分类号： G11C5/14
CPC分类号： G11C29/50 , G11C7/18 , G11C7/22 , G11C29/02 , G11C29/023 , G11C29/026 , G11C29/028 , G11C29/50012
摘要： In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.
摘要翻译：在一个实施例中，存储器块包括一个或多个位线，每个位线包括两个或更多个单元。每个位线中的每个单元具有与耦合到位线的读出放大器的距离，并且一个或多个位线中的每一个中的每一个中的一个或多个单元中的每个单元具有根据单元的距离特别设置的延迟从耦合到位线的读出放大器。

4. 发明申请

US20070195616A1 Setting One or More Delays of One or More Cells in a Memory Block to Improve One or More Characteristics of the Memory Block 失效
标题翻译：设置内存块中一个或多个单元的一个或多个延迟，以改善内存块的一个或多个特性
公开(公告)号：US20070195616A1
公开(公告)日：2007-08-23
申请号：US11673245
申请日：2007-02-09
申请人： Farzan Fallah , Behnam Amelifard , Massoud Pedram
发明人： Farzan Fallah , Behnam Amelifard , Massoud Pedram
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C7/18 , G11C7/22 , G11C29/02 , G11C29/023 , G11C29/026 , G11C29/028 , G11C29/50012
摘要： In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.
摘要翻译：在一个实施例中，存储器块包括一个或多个位线，每个位线包括两个或更多个单元。每个位线中的每个单元具有与耦合到位线的读出放大器的距离，并且一个或多个位线中的每一个中的每一个中的一个或多个单元中的每个单元具有根据单元的距离特别设置的延迟从耦合到位线的读出放大器。

5. 发明申请

US20130191679A1 DUAL MODE CLOCK/DATA RECOVERY CIRCUIT 有权
标题翻译：双模式时钟/数据恢复电路
公开(公告)号：US20130191679A1
公开(公告)日：2013-07-25
申请号：US13420800
申请日：2012-03-15
申请人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
发明人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
IPC分类号： G06F1/24
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

6. 发明申请

US20130120020A1 ADAPTIVE OUTPUT SWING DRIVER 审中-公开
标题翻译：自适应输出开关驱动器
公开(公告)号：US20130120020A1
公开(公告)日：2013-05-16
申请号：US13294482
申请日：2011-11-11
申请人： Miao Li , Behnam Amelifard , Xiaohua Kong , Nam V. Dang
发明人： Miao Li , Behnam Amelifard , Xiaohua Kong , Nam V. Dang
IPC分类号： H03K19/003
CPC分类号： H03K19/018564 , H03K19/01855 , H04L25/0264
摘要： An adjustable gain line driver receives an input signal and a gain control signal and outputs a signal with a swing, and the swing is measured to generate a swing measurement signal. A target swing signal is generated having a target swing, and the target swing signal is measured to generate a target swing reference signal. The swing measurement signal is compared to the target swing reference control signal and a counter generating the gain control signal is incremented until the measurement signal meets the target swing reference signal. Optionally a reset signal resets the counter, and the gain control signal, at predetermined events.
摘要翻译：可调增益线驱动器接收输入信号和增益控制信号并输出具有摆幅的信号，并且测量摆动以产生摆动测量信号。产生具有目标摆动的目标摆动信号，并且测量目标摆动信号以产生目标摆动参考信号。将摆动测量信号与目标摆动参考控制信号进行比较，生成增益控制信号的计数器递增，直到测量信号满足目标摆动参考信号为止。可选地，复位信号在预定事件时复位计数器和增益控制信号。

7. 发明授权

US07447101B2 PG-gated data retention technique for reducing leakage in memory cells 失效
标题翻译：用于减少存储单元泄漏的PG门控数据保留技术
公开(公告)号：US07447101B2
公开(公告)日：2008-11-04
申请号：US11615422
申请日：2006-12-22
申请人： Farzan Fallah , Behnam Amelifard , Massoud Pedram
发明人： Farzan Fallah , Behnam Amelifard , Massoud Pedram
IPC分类号： G11C5/14 , G11C11/00
CPC分类号： G11C11/417
摘要： A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept a ground. In one embodiment, the method includes forming the cell to accept selectively applied external voltages, wherein the external voltages are selected to minimize leakage current in the cell. In another embodiment, the method includes forming at least one of the first and the second transistors to have a channel width and/or a threshold voltage selected to minimize a total leakage current in the cell.
摘要翻译：形成存储单元的方法包括将存储单元的电源轨和可操作以接受电源电压的节点之间的第一晶体管耦合。该方法还包括将第二晶体管耦合在电池的接地导轨和可操作以接受接地的节点之间。在一个实施例中，该方法包括形成电池以接受选择性地施加的外部电压，其中选择外部电压以最小化电池中的泄漏电流。在另一个实施例中，该方法包括形成第一和第二晶体管中的至少一个以具有选择的沟道宽度和/或阈值电压以最小化单元中的总泄漏电流。

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