会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • TAIL-BITING CONVOLUTIONAL DECODING
    • 尾随转换解码
    • US20110280345A1
    • 2011-11-17
    • US12778605
    • 2010-05-12
    • Dung N. DoanJack K. WolfYongbin Wei
    • Dung N. DoanJack K. WolfYongbin Wei
    • H04L27/06
    • H03M13/413H03M13/6525
    • Methods and apparatuses for enhanced processing of received channels in a mobile communications system is described. Particularly, convolutionally encoded tail biting data in a mobile communications system is efficiently decoding by replicating the received encoded signal N times, where N equals a number of iterations. A Viterbi decoding algorithm is applied and a most likely survivor path is obtained. The ensuing decoding window is set as a fixed decoding window and placed at a mid-section of the most likely survivor path. Simulations have shown codeword accuracy to be comparable to MLSE with less complexity. A high degree of accuracy has been obtained for N=3.
    • 描述了用于移动通信系统中的接收信道的增强处理的方法和装置。 特别地,在移动通信系统中卷积编码的尾巴数据通过复制所接收的编码信号N次而有效地进行解码,其中N等于迭代次数。 应用维特比解码算法,获得最可能的幸存路径。 随后的解码窗口被设置为固定解码窗口并且被放置在最可能的幸存路径的中间部分。 仿真结果表明,码字精度与MLSE相当,复杂度较低。 对于N = 3,获得了高度的准确度。
    • 3. 发明授权
    • Trellis encoder and decoder based upon punctured rate 1/2 convolutional
codes
    • 网格编码器和解码器基于穿孔率+ E,fra 1/2 + EE卷积码
    • US5633881A
    • 1997-05-27
    • US368738
    • 1995-01-04
    • Ephraim ZehaviJack K. Wolf
    • Ephraim ZehaviJack K. Wolf
    • H03M13/25H04L1/00G06F11/10
    • H04L1/0068H03M13/25H03M13/256H03M13/3961H03M13/6362H04L1/0054H04L1/0059H04L1/006
    • An encoder for encoding data as trellis coded data and a decoder for decoding the trellis coded data. The encoder uses a rate 1/2 convolutional encoder punctured to a rate k/n to produce n symbols from k input bits. The symbols are converted by a converter to sets of p symbols and provided to an interleaver. In the interleaver certain ones of the symbols are delayed. Symbol sets are output from the interleaver to a 2.sup.P -ary modem for modulation and transmission. The decoder uses a modem for providing from the modulated data sets of p symbols. A deinterleaver delays certain ones of the symbols to achieve time alignment of the originally interleaved symbols. The sets of time aligned symbols are provided to metric calculators for computing signal metrics which are provided to a converter for providing n sets of metrics to a metric decoder. The metric decoder computes from the n sets of metrics an estimate of the encoded k data bits.
    • 用于将数据编码为网格编码数据的编码器和用于解码网格编码数据的解码器。 编码器使用从速率k / n穿过的速率+ E,fra 1/2 + EE卷积编码器,从k个输入位产生n个符号。 符号由转换器转换成p个符号的集合并提供给交织器。 在交织器中某些符号被延迟。 符号集从交织器输出到用于调制和传输的2P型调制解调器。 解码器使用调制解调器从p符号的调制数据集中提供。 解交织器延迟某些符号以实现原始交织符号的时间对准。 将时间对齐符号的集合提供给度量计算器,用于计算提供给转换器的信号度量,以向度量解码器提供n组度量。 度量解码器从n个度量值计算编码的k个数据比特的估计。
    • 5. 发明授权
    • Method and an apparatus for use of codes in multicast transmission
    • 多播传输中使用代码的方法和装置
    • US08656246B2
    • 2014-02-18
    • US09835903
    • 2001-04-16
    • Nagabhushana T. SindhushayanaJack K. Wolf
    • Nagabhushana T. SindhushayanaJack K. Wolf
    • H03M13/00
    • H04L12/1877H04L1/0045H04L1/0065H04L1/0068H04L12/189H04L2001/0093H04W4/06H04W28/06
    • A method and apparatus for multicasting of a multi-packet message are disclosed. Data to be transmitted as a message are divided into N sets, each set being encoded to generate encoded data. A set of parity bits is separated from each of the N sets of encoded data. The N sets of separated parity bits are encoded by a systematic code with a predetermined distance S across the N sets, resulting in N′ parity-bit packets. The N′ parity-bit packets are encoded with a code that is selected so that each receiving station decodes the N′ parity-bit packets with a high probability. The N-packet message, comprising the N sets of encoded data less the separated bits, and the N′ packets are multicasted. If less than S packets of the N-packet message fail to decode at a receiving station, the receiving station recovers all N packets using the N′ packets.
    • 公开了一种用于组播多分组消息的方法和装置。 作为消息传送的数据被划分为N组,每组被编码以产生编码数据。 一组奇偶校验位与N组编码数据中的每一个分离。 N组分离的奇偶校验位由跨越N组的预定距离S的系统代码编码,导致N个奇偶校验位分组。 N个奇偶校验位分组用选择的代码编码,使得每个接收站以高概率解码N个奇偶校验位分组。 包括N组编码数据少于分离比特的N分组消息和N'分组被多播。 如果N-packet消息中的S包少于在接收站解码,则接收站使用N'包恢复所有N个包。
    • 6. 发明授权
    • SerDes power throttling as a function of detected error rate
    • SerDes功率节流作为检测到的错误率的函数
    • US08578222B2
    • 2013-11-05
    • US13029934
    • 2011-02-17
    • Dexter T ChunJack K WolfJungwon SuhTirdad Sowlati
    • Dexter T ChunJack K WolfJungwon SuhTirdad Sowlati
    • G06F11/00
    • H04L12/12H04L1/0001H04L1/0036H04L25/02H04W52/0209Y02D70/00
    • A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.
    • 系统涉及从第一集成电路(IC)到第二IC的第一SerDes链路以及从第二IC到第一IC的第二链路。 调整第一链路的电路中的功率消耗设置以控制功率消耗,使得第一链路的误码率保持在范围的下限基本上大于零的范围内。 调整用于第二链路的电路中的功率消耗设置以控制功率消耗,使得第二链路的误码率保持在范围内,其范围的下限基本上大于零。 在一个示例中,第二IC中的电路检测第一链路中的错误并通过第二链路报告。 第一个IC使用报告的信息来确定第一个链路的误码率。
    • 7. 发明申请
    • SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE
    • 作为检测到的错误率的功能将功率节制作为电源
    • US20120216084A1
    • 2012-08-23
    • US13029934
    • 2011-02-17
    • Dexter T. ChunJack K. WolfJungwon SuhTirdad Sowlati
    • Dexter T. ChunJack K. WolfJungwon SuhTirdad Sowlati
    • G06F11/00
    • H04L12/12H04L1/0001H04L1/0036H04L25/02H04W52/0209Y02D70/00
    • A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.
    • 系统涉及从第一集成电路(IC)到第二IC的第一SerDes链路以及从第二IC到第一IC的第二链路。 调整第一链路的电路中的功率消耗设置以控制功率消耗,使得第一链路的误码率保持在范围的下限基本上大于零的范围内。 调整用于第二链路的电路中的功率消耗设置以控制功率消耗,使得第二链路的误码率保持在范围内,其范围的下限基本上大于零。 在一个示例中,第二IC中的电路检测第一链路中的错误并通过第二链路报告。 第一个IC使用报告的信息来确定第一个链路的误码率。