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1. 发明授权

US08839020B2 Dual mode clock/data recovery circuit 有权
标题翻译：双模时钟/数据恢复电路
公开(公告)号：US08839020B2
公开(公告)日：2014-09-16
申请号：US13420800
申请日：2012-03-15
申请人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
发明人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
IPC分类号： G06F1/04 , G06F1/12 , H03L7/00 , H04B7/212 , H04L12/28 , H04J3/06 , H04L7/00 , H04B1/16 , G06F15/16
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

2. 发明申请

US20130191679A1 DUAL MODE CLOCK/DATA RECOVERY CIRCUIT 有权
标题翻译：双模式时钟/数据恢复电路
公开(公告)号：US20130191679A1
公开(公告)日：2013-07-25
申请号：US13420800
申请日：2012-03-15
申请人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
发明人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
IPC分类号： G06F1/24
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

3. 发明申请

US20120109356A1 Method and Digital Circuit for Recovering a Clock and Data from an Input Signal Using a Digital Frequency Detection 有权
标题翻译：使用数字频率检测从输入信号中恢复时钟和数据的方法和数字电路
公开(公告)号：US20120109356A1
公开(公告)日：2012-05-03
申请号：US12938405
申请日：2010-11-03
申请人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
发明人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
IPC分类号： G01R13/02 , G06F19/00 , H03L7/06
CPC分类号： H04L7/033 , H04L7/0337
摘要： In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.
摘要翻译：在特定实施例中，数字电路包括频率检测电路，其可操作以比较与接收信号的连续采样之间的转换有关的信息。频率检测电路进一步操作以产生控制信号，以响应于具有相同值的预定数量的顺序样本来减小接收信号的采样率。该数字电路还包括一个数字相位检测器，可操作以提供与频率检测电路的连续样本之间的转换有关的信息。

4. 发明授权

US08798217B2 Method and digital circuit for recovering a clock and data from an input signal using a digital frequency detection 有权
标题翻译：用于使用数字频率检测从输入信号中恢复时钟和数据的方法和数字电路
公开(公告)号：US08798217B2
公开(公告)日：2014-08-05
申请号：US12938405
申请日：2010-11-03
申请人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
发明人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H04L7/0337
摘要： In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.
摘要翻译：在特定实施例中，数字电路包括频率检测电路，其可操作以比较与接收信号的连续采样之间的转换有关的信息。频率检测电路进一步操作以产生控制信号，以响应于具有相同值的预定数量的顺序样本来减小接收信号的采样率。该数字电路还包括一个数字相位检测器，可操作以提供与频率检测电路的连续样本之间的转换有关的信息。

5. 发明申请

US20130120020A1 ADAPTIVE OUTPUT SWING DRIVER 审中-公开
标题翻译：自适应输出开关驱动器
公开(公告)号：US20130120020A1
公开(公告)日：2013-05-16
申请号：US13294482
申请日：2011-11-11
申请人： Miao Li , Behnam Amelifard , Xiaohua Kong , Nam V. Dang
发明人： Miao Li , Behnam Amelifard , Xiaohua Kong , Nam V. Dang
IPC分类号： H03K19/003
CPC分类号： H03K19/018564 , H03K19/01855 , H04L25/0264
摘要： An adjustable gain line driver receives an input signal and a gain control signal and outputs a signal with a swing, and the swing is measured to generate a swing measurement signal. A target swing signal is generated having a target swing, and the target swing signal is measured to generate a target swing reference signal. The swing measurement signal is compared to the target swing reference control signal and a counter generating the gain control signal is incremented until the measurement signal meets the target swing reference signal. Optionally a reset signal resets the counter, and the gain control signal, at predetermined events.
摘要翻译：可调增益线驱动器接收输入信号和增益控制信号并输出具有摆幅的信号，并且测量摆动以产生摆动测量信号。产生具有目标摆动的目标摆动信号，并且测量目标摆动信号以产生目标摆动参考信号。将摆动测量信号与目标摆动参考控制信号进行比较，生成增益控制信号的计数器递增，直到测量信号满足目标摆动参考信号为止。可选地，复位信号在预定事件时复位计数器和增益控制信号。

6. 发明申请

US20130187717A1 RECEIVER EQUALIZATION CIRCUIT 审中-公开
标题翻译：接收器均衡电路
公开(公告)号：US20130187717A1
公开(公告)日：2013-07-25
申请号：US13405468
申请日：2012-02-27
申请人： Glenn A. Murphy , Nam V. Dang , Tirdad Sowlati , Xiaohua Kong
发明人： Glenn A. Murphy , Nam V. Dang , Tirdad Sowlati , Xiaohua Kong
IPC分类号： H03F3/16
CPC分类号： H03F3/3022 , H03F1/483
摘要： A receiver equalization circuit includes a first output transistor having a gate coupled to an input signal. The receiver equalization circuit may also include a second output transistor having a drain coupled to a drain of the first output transistor. The receiver equalization circuit may also include a resistor coupled between a gate and a drain of the second output transistor to provide a direct current (DC) bias to the gate of the second output transistor. The receiver equalization circuit may further include a feed-through capacitor coupled between the gate of the second output transistor and an input signal source. The feed-through capacitor feeds the input signal to the gate of the second output transistor when a frequency of the input signal is above a predetermined threshold. The feed-through capacitor and the resistor define a signal gain amplification point.
摘要翻译：接收机均衡电路包括具有耦合到输入信号的栅极的第一输出晶体管。接收机均衡电路还可以包括具有耦合到第一输出晶体管的漏极的漏极的第二输出晶体管。接收机均衡电路还可以包括耦合在第二输出晶体管的栅极和漏极之间的电阻器，以向第二输出晶体管的栅极提供直流（DC）偏置。接收机均衡电路还可以包括耦合在第二输出晶体管的栅极和输入信号源之间的馈通电容器。当输入信号的频率高于预定阈值时，馈通电容器将输入信号馈送到第二输出晶体管的栅极。馈通电容和电阻定义了信号增益放大点。

7. 发明申请

US20130216014A1 AUTOMATIC DETECTION AND COMPENSATION OF FREQUENCY OFFSET IN POINT-TO-POINT COMMUNICATION 有权
标题翻译：点对点通信中频率偏移的自动检测和补偿
公开(公告)号：US20130216014A1
公开(公告)日：2013-08-22
申请号：US13401020
申请日：2012-02-21
申请人： Xiaohua Kong , Zhi Zhu , Nam V. Dang
发明人： Xiaohua Kong , Zhi Zhu , Nam V. Dang
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/081 , H04L7/0025 , H04L7/033
摘要： Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock operating at a second frequency. A master phase-locked loop (PLL) comprising a first gated voltage controlled oscillator (GVCO) is configured to align the phases of reference clock and the input data, and provide phase error information and a recovered clock. A second GVCO is controlled by the recovered clock to sample the input data. A frequency alignment loop comprising a feedback path from the second GVCO to the master PLL is configured to use the phase error information to correct a frequency offset between the first frequency and the second frequency.
摘要翻译：自动检测和补偿点对点通信中频偏的系统和方法。突发模式时钟和数据恢复（CDR）系统包括以第一频率接收的输入数据和以第二频率工作的参考时钟。包括第一门控压控振荡器（GVCO）的主锁相环（PLL）被配置为对准参考时钟和输入数据的相位，并提供相位误差信息和恢复的时钟。第二个GVCO由恢复的时钟控制，以对输入数据进行采样。包括从第二GVCO到主PLL的反馈路径的频率对准环路被配置为使用相位误差信息来校正第一频率和第二频率之间的频率偏移。

8. 发明授权

US08742864B2 Method and digital circuit for generating a waveform from stored digital values 失效
标题翻译：用于从存储的数字值产生波形的方法和数字电路
公开(公告)号：US08742864B2
公开(公告)日：2014-06-03
申请号：US12939206
申请日：2010-11-04
申请人： Zhi Zhu , Xiaohua Kong , Nam V. Dang
发明人： Zhi Zhu , Xiaohua Kong , Nam V. Dang
IPC分类号： H03C3/06
CPC分类号： H03L7/1976
摘要： In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path.
摘要翻译：在一个具体实施例中，一种方法包括基于存储的数字值来调节在锁相环电路的反馈路径上的分频器的输入，该数字值表示施加到调制器电路的基于时间的波形的一部分。基于反馈路径的输出检索存储的数字值。

9. 发明申请

US20130120036A1 APPARATUS AND METHOD FOR RECOVERING BURST-MODE PULSE WIDTH MODULATION (PWM) AND NON-RETURN-TO-ZERO (NRZ) DATA 有权
公开(公告)号：US20130120036A1
公开(公告)日：2013-05-16
申请号：US13363410
申请日：2012-02-01
申请人： Zhi Zhu , Xiaohua Kong , Nam V. Dang
发明人： Zhi Zhu , Xiaohua Kong , Nam V. Dang
IPC分类号： H03L7/08
CPC分类号： H03L7/0802 , H03L7/0805 , H03L7/0807 , H03L7/0995 , H04L7/0276 , H04L7/0338
摘要： A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

10. 发明授权

US08542039B2 High-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications 有权
标题翻译：高速预驱动器和电压电平转换器，内置去加重HDMI传输应用
公开(公告)号：US08542039B2
公开(公告)日：2013-09-24
申请号：US13294273
申请日：2011-11-11
申请人： Miao Li , Zhi Zhu , Xiaohua Kong , Nam V. Dang
发明人： Miao Li , Zhi Zhu , Xiaohua Kong , Nam V. Dang
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018514 , H04L25/0272 , H04L25/0286
摘要： In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.
摘要翻译：在一个例子中，提供了一个高速预驱动器和电压电平转换器，内置去加重HDMI传输应用。示例性集成电路包括串行器，耦合以从串行器接收差分输入的预驱动器和驱动器。预驱动器包括全部p型金属氧化物硅（PMOS）交叉耦合电平转换器，其包括四个PMOS晶体管和两个去加重PMOS晶体管，其形成耦合到交叉耦合电平的输出的去加重抽头转换器。驱动器耦合到预驱动器输出，并被配置为从前驱动器接收差分输入。

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