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1. 发明授权

US08503156B2 Methods of processing semiconductor substrates, electrostatic carriers for retaining substrates for processing, and assemblies comprising electrostatic carriers having substrates electrostatically bonded thereto 有权
公开(公告)号：US08503156B2
公开(公告)日：2013-08-06
申请号：US13169915
申请日：2011-06-27
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： H01L21/683
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.

2. 发明授权

US07989022B2 Methods of processing substrates, electrostatic carriers for retaining substrates for processing, and assemblies comprising electrostatic carriers having substrates electrostatically bonded thereto 有权
标题翻译：处理基板的方法，用于保持用于处理的基板的静电载体，以及包括静电载体的组件，所述静电载体具有静电键合的基板
公开(公告)号：US07989022B2
公开(公告)日：2011-08-02
申请号：US11780628
申请日：2007-07-20
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： C23C16/00
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.
摘要翻译：处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。导体从物理接触暴露的导电电极去除。电介质材料施加在导电电极上。在静电接触静电载体的同时对衬底进行处理。在一个实施例中，将导体强制通过介电材料，其被接收在静电载体的导电电极上，以与导电电极物理接触导体，以使基板静电地接合到静电载体上。在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。还公开了用于保持用于加工的基材和这种组件的静电载体。

3. 发明申请

US20110253042A1 Methods of Processing Semiconductor Substrates, Electrostatic Carriers for Retaining Substrates for Processing, and Assemblies Comprising Electrostatic Carriers Having Substrates Electrostatically Bonded Thereto 有权
标题翻译：处理半导体基板的方法，用于保持用于加工的基板的静电载体和包括静电载体的组件，其具有静电粘合的基板
公开(公告)号：US20110253042A1
公开(公告)日：2011-10-20
申请号：US13169915
申请日：2011-06-27
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： B05C13/00
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.
摘要翻译：处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。导体从物理接触暴露的导电电极去除。电介质材料施加在导电电极上。在静电接触静电载体的同时对衬底进行处理。在一个实施例中，将导体强制通过介电材料，其被接收在静电载体的导电电极上，以与导电电极物理接触导体，以使基板静电地接合到静电载体上。在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。还公开了用于保持用于加工的基材和这种组件的静电载体。

4. 发明申请

US20090022901A1 Methods of Processing Substrates, Electrostatic Carriers for Retaining Substrates for Processing, and Assemblies Comprising Electrostatic Carriers Having Substrates Electrostatically Bonded Thereto 有权
标题翻译：处理基板的方法，用于保留用于加工的基板的静电载体，以及包括具有基底静电粘合的静电载体的组件
公开(公告)号：US20090022901A1
公开(公告)日：2009-01-22
申请号：US11780628
申请日：2007-07-20
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： B05D1/32 , B05B5/025
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.
摘要翻译：处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。导体从物理接触暴露的导电电极去除。电介质材料施加在导电电极上。在静电接触静电载体的同时对衬底进行处理。在一个实施例中，将导体强制通过电介质材料，该电介质材料被接纳在静电载体的导电电极上，以使导体与导电电极物理接触以将基底静电地接合到静电载体上。在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。还公开了用于保持用于加工的基材和这种组件的静电载体。

5. 发明申请

US20120094443A1 PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS 有权
标题翻译：用于微电子和相关系统和方法的通过3D互连
公开(公告)号：US20120094443A1
公开(公告)日：2012-04-19
申请号：US13335619
申请日：2011-12-22
申请人： David S. Pratt , Kyle K. Kirby , Dewali Ray
发明人： David S. Pratt , Kyle K. Kirby , Dewali Ray
IPC分类号： H01L21/50 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/043 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/051 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2924/01019 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
摘要翻译：本文公开了直通3D互连和包括这种互连的堆叠管芯的微电子管芯和系统。在一个实施例中，堆叠管芯的系统包括具有衬底，金属衬底焊盘和电耦合到衬底焊盘的第一集成电路的第一微电子管芯。直通3D互连在衬底的前侧和后侧之间延伸，包括通过衬底焊盘。所述直通互连件与所述衬底焊盘电隔离并且电耦合到附接到所述衬底的背侧的第二微电子管芯的第二集成电路。在另一个实施例中，第一集成电路是第一存储器件，第二集成电路是第二存储器件，并且系统使用直通互连作为到第二存储器件的独立通信路径的一部分。

6. 发明授权

US08084854B2 Pass-through 3D interconnect for microelectronic dies and associated systems and methods 有权
标题翻译：用于微电子管芯的直通3D互连及相关系统和方法
公开(公告)号：US08084854B2
公开(公告)日：2011-12-27
申请号：US11966824
申请日：2007-12-28
申请人： David S. Pratt , Kyle K. Kirby , Dewali Ray
发明人： David S. Pratt , Kyle K. Kirby , Dewali Ray
IPC分类号： H01L23/04
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/043 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/051 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2924/01019 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
摘要翻译：本文公开了直通3D互连和包括这种互连的堆叠管芯的微电子管芯和系统。在一个实施例中，堆叠管芯的系统包括具有衬底，金属衬底焊盘和电耦合到衬底焊盘的第一集成电路的第一微电子管芯。直通3D互连在衬底的前侧和后侧之间延伸，包括通过衬底焊盘。所述直通互连件与所述衬底焊盘电隔离并且电耦合到附接到所述衬底的背侧的第二微电子管芯的第二集成电路。在另一个实施例中，第一集成电路是第一存储器件，第二集成电路是第二存储器件，并且系统使用直通互连作为到第二存储器件的独立通信路径的一部分。

7. 发明申请

US20090166846A1 PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS 有权
标题翻译：用于微电子和相关系统和方法的通过3D互连
公开(公告)号：US20090166846A1
公开(公告)日：2009-07-02
申请号：US11966824
申请日：2007-12-28
申请人： David S. Pratt , Kyle K. Kirby , Dewali Ray
发明人： David S. Pratt , Kyle K. Kirby , Dewali Ray
IPC分类号： H01L21/50 , H01L23/02
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/043 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/051 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2924/01019 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
摘要翻译：本文公开了直通3D互连和包括这种互连的堆叠管芯的微电子管芯和系统。在一个实施例中，堆叠管芯的系统包括具有衬底，金属衬底焊盘和电耦合到衬底焊盘的第一集成电路的第一微电子管芯。直通3D互连在衬底的前侧和后侧之间延伸，包括通过衬底焊盘。所述直通互连件与所述衬底焊盘电隔离并且电耦合到附接到所述衬底的背侧的第二微电子管芯的第二集成电路。在另一个实施例中，第一集成电路是第一存储器件，第二集成电路是第二存储器件，并且系统使用直通互连作为到第二存储器件的独立通信路径的一部分。

8. 发明授权

US09209158B2 Pass-through 3D interconnect for microelectronic dies and associated systems and methods 有权
标题翻译：用于微电子管芯的直通3D互连及相关系统和方法
公开(公告)号：US09209158B2
公开(公告)日：2015-12-08
申请号：US13335619
申请日：2011-12-22
申请人： David S. Pratt , Kyle K. Kirby , Dewali Ray
发明人： David S. Pratt , Kyle K. Kirby , Dewali Ray
IPC分类号： H01L21/768 , H01L25/065 , H01L25/00 , H01L25/18
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/043 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/051 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2924/01019 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
摘要翻译：本文公开了直通3D互连和包括这种互连的堆叠管芯的微电子管芯和系统。在一个实施例中，堆叠管芯的系统包括具有衬底，金属衬底焊盘和电耦合到衬底焊盘的第一集成电路的第一微电子管芯。直通3D互连在衬底的前侧和后侧之间延伸，包括通过衬底焊盘。所述直通互连件与所述衬底焊盘电隔离并且电耦合到附接到所述衬底的背侧的第二微电子管芯的第二集成电路。在另一个实施例中，第一集成电路是第一存储器件，第二集成电路是第二存储器件，并且系统使用直通互连作为到第二存储器件的独立通信路径的一部分。

9. 发明授权

US07960829B2 Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates 有权
标题翻译：用于减薄半导体衬底和用于支撑薄化半导体衬底的支撑结构
公开(公告)号：US07960829B2
公开(公告)日：2011-06-14
申请号：US11216617
申请日：2005-08-31
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
IPC分类号： H01L23/12
CPC分类号： G03F7/0037 , B33Y30/00 , B33Y70/00 , B33Y80/00 , G03F7/0047
摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member that substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.
摘要翻译：用于半导体衬底的减薄或后研磨以及在半导体衬底的后变薄处理期间的支撑结构包括基本上沿着半导体衬底的外周延伸并围绕半导体衬底的外周延伸的部分，以使半导体衬底基板具有刚性。支撑结构可以被构造为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。

10. 发明授权

US07956443B2 Through-wafer interconnects for photoimager and memory wafers 有权
标题翻译：用于光刻机和存储晶圆的透晶片互连
公开(公告)号：US07956443B2
公开(公告)日：2011-06-07
申请号：US12725724
申请日：2010-03-17
申请人： Salman Akram , Charles M. Watkins , Mark Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
发明人： Salman Akram , Charles M. Watkins , Mark Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
IPC分类号： H01L23/485
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译：公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

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