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1. 发明授权

US08503156B2 Methods of processing semiconductor substrates, electrostatic carriers for retaining substrates for processing, and assemblies comprising electrostatic carriers having substrates electrostatically bonded thereto 有权
公开(公告)号：US08503156B2
公开(公告)日：2013-08-06
申请号：US13169915
申请日：2011-06-27
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： H01L21/683
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.

2. 发明授权

US07989022B2 Methods of processing substrates, electrostatic carriers for retaining substrates for processing, and assemblies comprising electrostatic carriers having substrates electrostatically bonded thereto 有权
标题翻译：处理基板的方法，用于保持用于处理的基板的静电载体，以及包括静电载体的组件，所述静电载体具有静电键合的基板
公开(公告)号：US07989022B2
公开(公告)日：2011-08-02
申请号：US11780628
申请日：2007-07-20
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： C23C16/00
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.
摘要翻译：处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。导体从物理接触暴露的导电电极去除。电介质材料施加在导电电极上。在静电接触静电载体的同时对衬底进行处理。在一个实施例中，将导体强制通过介电材料，其被接收在静电载体的导电电极上，以与导电电极物理接触导体，以使基板静电地接合到静电载体上。在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。还公开了用于保持用于加工的基材和这种组件的静电载体。

3. 发明申请

US20110253042A1 Methods of Processing Semiconductor Substrates, Electrostatic Carriers for Retaining Substrates for Processing, and Assemblies Comprising Electrostatic Carriers Having Substrates Electrostatically Bonded Thereto 有权
标题翻译：处理半导体基板的方法，用于保持用于加工的基板的静电载体和包括静电载体的组件，其具有静电粘合的基板
公开(公告)号：US20110253042A1
公开(公告)日：2011-10-20
申请号：US13169915
申请日：2011-06-27
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： B05C13/00
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.
摘要翻译：处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。导体从物理接触暴露的导电电极去除。电介质材料施加在导电电极上。在静电接触静电载体的同时对衬底进行处理。在一个实施例中，将导体强制通过介电材料，其被接收在静电载体的导电电极上，以与导电电极物理接触导体，以使基板静电地接合到静电载体上。在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。还公开了用于保持用于加工的基材和这种组件的静电载体。

4. 发明申请

US20090022901A1 Methods of Processing Substrates, Electrostatic Carriers for Retaining Substrates for Processing, and Assemblies Comprising Electrostatic Carriers Having Substrates Electrostatically Bonded Thereto 有权
标题翻译：处理基板的方法，用于保留用于加工的基板的静电载体，以及包括具有基底静电粘合的静电载体的组件
公开(公告)号：US20090022901A1
公开(公告)日：2009-01-22
申请号：US11780628
申请日：2007-07-20
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： B05D1/32 , B05B5/025
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.
摘要翻译：处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。导体从物理接触暴露的导电电极去除。电介质材料施加在导电电极上。在静电接触静电载体的同时对衬底进行处理。在一个实施例中，将导体强制通过电介质材料，该电介质材料被接纳在静电载体的导电电极上，以使导体与导电电极物理接触以将基底静电地接合到静电载体上。在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。还公开了用于保持用于加工的基材和这种组件的静电载体。

5. 发明申请

US20120094443A1 PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS 有权
标题翻译：用于微电子和相关系统和方法的通过3D互连
公开(公告)号：US20120094443A1
公开(公告)日：2012-04-19
申请号：US13335619
申请日：2011-12-22
申请人： David S. Pratt , Kyle K. Kirby , Dewali Ray
发明人： David S. Pratt , Kyle K. Kirby , Dewali Ray
IPC分类号： H01L21/50 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/043 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/051 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2924/01019 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
摘要翻译：本文公开了直通3D互连和包括这种互连的堆叠管芯的微电子管芯和系统。在一个实施例中，堆叠管芯的系统包括具有衬底，金属衬底焊盘和电耦合到衬底焊盘的第一集成电路的第一微电子管芯。直通3D互连在衬底的前侧和后侧之间延伸，包括通过衬底焊盘。所述直通互连件与所述衬底焊盘电隔离并且电耦合到附接到所述衬底的背侧的第二微电子管芯的第二集成电路。在另一个实施例中，第一集成电路是第一存储器件，第二集成电路是第二存储器件，并且系统使用直通互连作为到第二存储器件的独立通信路径的一部分。

6. 发明授权

US08084854B2 Pass-through 3D interconnect for microelectronic dies and associated systems and methods 有权
标题翻译：用于微电子管芯的直通3D互连及相关系统和方法
公开(公告)号：US08084854B2
公开(公告)日：2011-12-27
申请号：US11966824
申请日：2007-12-28
申请人： David S. Pratt , Kyle K. Kirby , Dewali Ray
发明人： David S. Pratt , Kyle K. Kirby , Dewali Ray
IPC分类号： H01L23/04
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/043 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/051 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2924/01019 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
摘要翻译：本文公开了直通3D互连和包括这种互连的堆叠管芯的微电子管芯和系统。在一个实施例中，堆叠管芯的系统包括具有衬底，金属衬底焊盘和电耦合到衬底焊盘的第一集成电路的第一微电子管芯。直通3D互连在衬底的前侧和后侧之间延伸，包括通过衬底焊盘。所述直通互连件与所述衬底焊盘电隔离并且电耦合到附接到所述衬底的背侧的第二微电子管芯的第二集成电路。在另一个实施例中，第一集成电路是第一存储器件，第二集成电路是第二存储器件，并且系统使用直通互连作为到第二存储器件的独立通信路径的一部分。

7. 发明申请

US20090166846A1 PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS 有权
标题翻译：用于微电子和相关系统和方法的通过3D互连
公开(公告)号：US20090166846A1
公开(公告)日：2009-07-02
申请号：US11966824
申请日：2007-12-28
申请人： David S. Pratt , Kyle K. Kirby , Dewali Ray
发明人： David S. Pratt , Kyle K. Kirby , Dewali Ray
IPC分类号： H01L21/50 , H01L23/02
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/043 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/051 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2924/01019 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
摘要翻译：本文公开了直通3D互连和包括这种互连的堆叠管芯的微电子管芯和系统。在一个实施例中，堆叠管芯的系统包括具有衬底，金属衬底焊盘和电耦合到衬底焊盘的第一集成电路的第一微电子管芯。直通3D互连在衬底的前侧和后侧之间延伸，包括通过衬底焊盘。所述直通互连件与所述衬底焊盘电隔离并且电耦合到附接到所述衬底的背侧的第二微电子管芯的第二集成电路。在另一个实施例中，第一集成电路是第一存储器件，第二集成电路是第二存储器件，并且系统使用直通互连作为到第二存储器件的独立通信路径的一部分。

8. 发明授权

US09209158B2 Pass-through 3D interconnect for microelectronic dies and associated systems and methods 有权
标题翻译：用于微电子管芯的直通3D互连及相关系统和方法
公开(公告)号：US09209158B2
公开(公告)日：2015-12-08
申请号：US13335619
申请日：2011-12-22
申请人： David S. Pratt , Kyle K. Kirby , Dewali Ray
发明人： David S. Pratt , Kyle K. Kirby , Dewali Ray
IPC分类号： H01L21/768 , H01L25/065 , H01L25/00 , H01L25/18
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/043 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/051 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2924/01019 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
摘要翻译：本文公开了直通3D互连和包括这种互连的堆叠管芯的微电子管芯和系统。在一个实施例中，堆叠管芯的系统包括具有衬底，金属衬底焊盘和电耦合到衬底焊盘的第一集成电路的第一微电子管芯。直通3D互连在衬底的前侧和后侧之间延伸，包括通过衬底焊盘。所述直通互连件与所述衬底焊盘电隔离并且电耦合到附接到所述衬底的背侧的第二微电子管芯的第二集成电路。在另一个实施例中，第一集成电路是第一存储器件，第二集成电路是第二存储器件，并且系统使用直通互连作为到第二存储器件的独立通信路径的一部分。

9. 发明申请

US20090029152A1 Wafer Bonding Using Nanoparticle Material 审中-公开
标题翻译：使用纳米粒子材料的晶圆贴合
公开(公告)号：US20090029152A1
公开(公告)日：2009-01-29
申请号：US11828075
申请日：2007-07-25
申请人： Changhan Yun , Dewali Ray
发明人： Changhan Yun , Dewali Ray
IPC分类号： B32B5/16 , B32B37/14
CPC分类号： B81C1/00269 , B81C2203/0118 , Y10T156/10 , Y10T428/256
摘要： A method of forming a MEMS device includes providing a first wafer having a MEMS structure in a first area and a second wafer having a second area, applying a metal nanoparticle material between the first wafer and the second wafer, and bonding a portion of the first wafer to a portion of the second wafer with the metal nanoparticle material so as to form a sealed area in the first area and the second area.
摘要翻译：形成MEMS器件的方法包括在第一区域中提供具有MEMS结构的第一晶片和具有第二区域的第二晶片，在第一晶片和第二晶片之间施加金属纳米颗粒材料，以及将第一将晶片与金属纳米颗粒材料连接到第二晶片的一部分，以在第一区域和第二区域中形成密封区域。

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