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1. 发明申请

US20110193174A1 Multiple Silicide Integration Structure and Method 有权
标题翻译：多重硅化物一体化结构与方法
公开(公告)号：US20110193174A1
公开(公告)日：2011-08-11
申请号：US12704296
申请日：2010-02-11
申请人： Der-Chyang Yeh , Hsing-Kuo Hsia , Hao-Hsun Lin , Chih-Ping Chao , Chin-Hao Su , Hsi-Kuei Cheng
发明人： Der-Chyang Yeh , Hsing-Kuo Hsia , Hao-Hsun Lin , Chih-Ping Chao , Chin-Hao Su , Hsi-Kuei Cheng
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/0623 , H01L21/28518 , H01L21/8249 , H01L29/45
摘要： A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.
摘要翻译：提供了一种提供多重硅化物整合的结构和方法。一个实施例包括在衬底上形成第一晶体管和第二晶体管。第一晶体管被掩蔽，并且在第二晶体管上形成第一硅化物区。然后对第二晶体管进行掩模，并且在第一晶体管上形成第二硅化物区域，从而允许在独立器件上形成器件特定的硅化物区域。

2. 发明授权

US08993393B2 Multiple silicide integration structure and method 有权
标题翻译：多硅化物整合结构与方法
公开(公告)号：US08993393B2
公开(公告)日：2015-03-31
申请号：US12704296
申请日：2010-02-11
申请人： Der-Chyang Yeh , Hsing-Kuo Hsia , Hao-Hsun Lin , Chih-Ping Chao , Chin-Hao Su , Hsi-Kuei Cheng
发明人： Der-Chyang Yeh , Hsing-Kuo Hsia , Hao-Hsun Lin , Chih-Ping Chao , Chin-Hao Su , Hsi-Kuei Cheng
IPC分类号： H01L29/72 , H01L21/8249 , H01L21/285 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/28518 , H01L21/8249 , H01L29/45
摘要： A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.
摘要翻译：提供了一种提供多重硅化物整合的结构和方法。一个实施例包括在衬底上形成第一晶体管和第二晶体管。第一晶体管被掩蔽，并且在第二晶体管上形成第一硅化物区。然后对第二晶体管进行掩模，并且在第一晶体管上形成第二硅化物区域，从而允许在独立器件上形成器件特定的硅化物区域。

3. 发明申请

US20110318898A1 HARD MASK FOR THIN FILM RESISTOR MANUFACTURE 有权
标题翻译：薄膜电阻器制造的硬掩模
公开(公告)号：US20110318898A1
公开(公告)日：2011-12-29
申请号：US12824495
申请日：2010-06-28
申请人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
发明人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01L28/24
摘要： Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.
摘要翻译：公开了制造诸如薄膜电阻器的集成电路器件的方法。一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成电阻层; 在所述电阻层上形成硬掩模层，其中所述硬掩模层包括所述电阻层上的阻挡层和所述阻挡层上的电介质层; 以及在所述硬掩模层中形成暴露所述电阻层的一部分的开口。

4. 发明授权

US08581347B2 Forming bipolar transistor through fast EPI-growth on polysilicon 有权
标题翻译：通过在多晶硅上快速EPI生长形成双极晶体管
公开(公告)号：US08581347B2
公开(公告)日：2013-11-12
申请号：US12841275
申请日：2010-07-22
申请人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
发明人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L21/8228 , H01L27/0623 , H01L27/0826
摘要： Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.
摘要翻译：提供了一种半导体器件，其包括形成在同一衬底上的第一晶体管和第二晶体管。第一晶体管包括第一集电极，第一基极和第一发射极。第一集电器包括设置在衬底中的第一掺杂阱。第一基底包括设置在衬底上方和第一掺杂阱上方的第一掺杂层。第一发射器包括设置在第一掺杂层的一部分上的掺杂元件。第二晶体管包括第二集电极，第二基极和第二发射极。第二集电体包括衬底的掺杂部分。第二基底包括设置在衬底中并在衬底的掺杂部分上方的第二掺杂阱。第二发射器包括设置在衬底上方和第二掺杂阱上方的第二掺杂层。

5. 发明授权

US08334579B2 Schottky diode 有权
标题翻译：肖特基二极管
公开(公告)号：US08334579B2
公开(公告)日：2012-12-18
申请号：US12899904
申请日：2010-10-07
申请人： Ping Chun Yeh , Der-Chyang Yeh , Chih-Ping Chao
发明人： Ping Chun Yeh , Der-Chyang Yeh , Chih-Ping Chao
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0692 , H01L29/1095 , H01L29/6606 , H01L29/66143 , H01L29/66212
摘要： An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。集成电路器件包括衬底，扩散源和与导电层接触的轻掺杂扩散区域。轻掺杂扩散区与导电层的结形成肖特基区。进行退火处理以形成轻掺杂扩散区域。退火处理使得集成电路器件的扩散源（例如，设置在衬底中的n阱）的掺杂剂扩散到衬底的区域中，从而形成轻掺杂扩散区域。

6. 发明申请

US20120086099A1 SCHOTTKY DIODE 有权
标题翻译：肖特基二极管
公开(公告)号：US20120086099A1
公开(公告)日：2012-04-12
申请号：US12899904
申请日：2010-10-07
申请人： Ping Chun Yeh , Der-Chyang Yeh , Chih-Ping Chao
发明人： Ping Chun Yeh , Der-Chyang Yeh , Chih-Ping Chao
IPC分类号： H01L29/872 , H01L21/04
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0692 , H01L29/1095 , H01L29/6606 , H01L29/66143 , H01L29/66212
摘要： An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。集成电路器件包括衬底，扩散源和与导电层接触的轻掺杂扩散区域。轻掺杂扩散区与导电层的结形成肖特基区。进行退火处理以形成轻掺杂扩散区域。退火处理使得集成电路器件的扩散源（例如，设置在衬底中的n阱）的掺杂剂扩散到衬底的区域中，从而形成轻掺杂扩散区域。

7. 发明申请

US20120018811A1 FORMING BIPOLAR TRANSISTOR THROUGH FAST EPI-GROWTH ON POLYSILICON 有权
标题翻译：形成双极晶体管通过快速增长在多晶硅上
公开(公告)号：US20120018811A1
公开(公告)日：2012-01-26
申请号：US12841275
申请日：2010-07-22
申请人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
发明人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L21/8228 , H01L27/0623 , H01L27/0826
摘要： Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.
摘要翻译：提供了一种半导体器件，其包括形成在同一衬底上的第一晶体管和第二晶体管。第一晶体管包括第一集电极，第一基极和第一发射极。第一集电器包括设置在衬底中的第一掺杂阱。第一基底包括设置在衬底上方和第一掺杂阱上方的第一掺杂层。第一发射器包括设置在第一掺杂层的一部分上的掺杂元件。第二晶体管包括第二集电极，第二基极和第二发射极。第二集电体包括衬底的掺杂部分。第二基底包括设置在衬底中并在衬底的掺杂部分上方的第二掺杂阱。第二发射器包括设置在衬底上方和第二掺杂阱上方的第二掺杂层。

8. 发明授权

US08080461B2 Method of making a thin film resistor 有权
标题翻译：制造薄膜电阻的方法
公开(公告)号：US08080461B2
公开(公告)日：2011-12-20
申请号：US12688083
申请日：2010-01-15
申请人： Der-Chyang Yeh , Hsun-Chung Kuang , Ming Chyi Liu , Chung-Yi Yu , Chih-Ping Chao , Alexander Kalnitsky
发明人： Der-Chyang Yeh , Hsun-Chung Kuang , Ming Chyi Liu , Chung-Yi Yu , Chih-Ping Chao , Alexander Kalnitsky
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L28/20 , H01L21/76801 , H01L21/76843 , H01L21/76864 , H01L21/76865 , H01L27/016 , H01L28/24
摘要： A method of making a thin film resistor includes: forming a doped region in a semiconductor substrate; forming a dielectric layer over the substrate; forming a thin film resistor over the dielectric layer; forming a contact hole in the dielectric layer before annealing the thin film resistor, wherein the contact hole exposes a portion of the doped region; and performing rapid thermal annealing on the thin film resistor after forming the contact hole.
摘要翻译：制造薄膜电阻器的方法包括：在半导体衬底中形成掺杂区域; 在所述衬底上形成介电层; 在介电层上形成薄膜电阻; 在退火所述薄膜电阻器之前，在所述电介质层中形成接触孔，其中所述接触孔暴露所述掺杂区域的一部分; 并且在形成接触孔之后对薄膜电阻器进行快速热退火。

9. 发明授权

US08334187B2 Hard mask for thin film resistor manufacture 有权
标题翻译：薄膜电阻制造的硬掩模
公开(公告)号：US08334187B2
公开(公告)日：2012-12-18
申请号：US12824495
申请日：2010-06-28
申请人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
发明人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L28/24
摘要： Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.
摘要翻译：公开了制造诸如薄膜电阻器的集成电路器件的方法。一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成电阻层; 在所述电阻层上形成硬掩模层，其中所述硬掩模层包括所述电阻层上的阻挡层和所述阻挡层上的电介质层; 以及在所述硬掩模层中形成暴露所述电阻层的一部分的开口。

10. 发明授权

US08847321B2 Cascode CMOS structure 有权
标题翻译： Cascode CMOS结构
公开(公告)号：US08847321B2
公开(公告)日：2014-09-30
申请号：US12766972
申请日：2010-04-26
申请人： Fu-Lung Hsueh , Chih-Ping Chao , Chewn-Pu Jou , Yung-Chow Peng , Harry-Hak-Lay Chuang , Kuo-Tung Sung
发明人： Fu-Lung Hsueh , Chih-Ping Chao , Chewn-Pu Jou , Yung-Chow Peng , Harry-Hak-Lay Chuang , Kuo-Tung Sung
IPC分类号： H01L29/78 , G06F17/50 , H01L27/088
CPC分类号： G06F17/5068 , G06F17/50 , G06F17/5009 , H01L27/088 , H01L27/0922
摘要： A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.
摘要翻译： MOS器件包括具有第一和第二触点的有源区。第一和第二栅极设置在第一和第二触点之间。第一门被设置成与第一接触相邻并且具有第三接触。第二栅极被设置成与第二触点相邻并且具有耦合到第三触点的第四触点。由有源区和第一栅极限定的晶体管具有第一阈值电压，并且由有源区和第二栅极限定的晶体管具有第二阈值电压。

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