专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2015023115A ショットキーダイオードを内蔵するＦＥＴ有权
标题翻译： FET INCORPORATING肖特基二极管
公开(公告)号：JP2015023115A
公开(公告)日：2015-02-02
申请号：JP2013149323
申请日：2013-07-18
申请人：株式会社豊田中央研究所 , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , Toyota Motor Corp , 株式会社デンソー , Denso Corp
发明人： WATANABE YUKIHIKO , AOI SACHIKO , TAKATANI HIDESHI , AKIBA ATSUYA
IPC分类号： H01L27/04 , H01L21/28 , H01L21/336 , H01L29/12 , H01L29/41 , H01L29/47 , H01L29/78 , H01L29/872
CPC分类号： H01L29/7806 , H01L21/049 , H01L21/0495 , H01L27/0255 , H01L29/0623 , H01L29/0692 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/66734 , H01L29/7813 , H01L29/872
摘要：【課題】ショットキーダイオードを内蔵しているFETであって、ショットキーダイオードの形成面積とFETの形成面積の比を自由に調整でき、破壊されにくい構造とする。【解決手段】長く延びているトレンチを利用する。トレンチの長さ方向において断続的に出現する位置にショットキー電極を介在させる。SiCに形成される熱酸化膜の成長速度が遅く、ポリシリコンに形成される熱酸化膜の成長速度が速いことを利用すると、ゲート電極とショットキー電極の間、ゲート電極とソース領域の間、ゲート電極とボディ領域の間、ゲート電極とドレイン領域の間には絶縁膜が形成されており、ショットキー電極とドレイン領域の間には絶縁膜が形成されていない構造を得ることができる。【選択図】図1
摘要翻译：要解决的问题：提供一种结合了肖特基二极管并且具有不太可能被破坏的结构的FET，其中肖特基二极管的形成面积与FET的形成面积的比率可以自由调节。解决方案：使用延长沟槽。肖特基电极插入在沟槽的长度方向上间断地出现的位置处。通过使用在SiC上形成的热氧化膜的生长速度慢，并且在多晶硅上形成的热氧化膜的生长速度快的事实，可以在栅电极和肖特基电极，栅电极和源极区之间，栅电极与体区之间以及栅电极和漏区之间的肖特基电极，但是在肖特基电极和漏极区之间不形成绝缘膜。

2. 发明专利

JP2005045123A Trench gate type semiconductor device and its manufacturing device 审中-公开
标题翻译： TRENCH门式半导体器件及其制造设备
公开(公告)号：JP2005045123A
公开(公告)日：2005-02-17
申请号：JP2003279293
申请日：2003-07-24
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , OKURA YASUTSUGU , KUROYANAGI AKIRA
IPC分类号： H01L29/41 , H01L21/336 , H01L29/417 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a trench gate type MOS FET of low ON resistance.
SOLUTION: An n
- -type drift region 2 and a p-channel region 3 are laminated one by one on an n
+ -type substrate 1. An n
+ -type source region 4 and a p
+ -type body region 5 are formed to a stripe in an upper surface of the p-channel region 3. A trench 7 passes through the p(n)-type channel region 3 and attains to the n
- -type drift region 2, and a gate 9 constituted of polycrystalline silicon is buried via a gate insulating film 8. The n
+ -type source region 4 and the p
+ -type body region 5 extend from the p(n)-type channel region 3 to a source electrode 20 and cross the trench 7. The upper surface of the gate 9 is located above the upper surface of the p-channel region 3. A layer insulating film 10 is inside the trench 7, and its upper surface is located below an opening of the trench 7. The source electrode 20, the n
+ -type source region 4 and the p
+ -type body region 5 are electrically connected each in a side wall of the trench 7.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供低导通电阻的沟槽栅型MOS FET。解决方案：将n - / SP>型漂移区2和p沟道区3逐层层叠在n + 型衬底1上.n 在p沟道区域3的上表面中形成有条纹的 + 型源极区域4和ap + 型体区域5.沟槽7通过 p（n）型沟道区3并达到n - SP型漂移区2，并且由多晶硅构成的栅极9通过栅极绝缘膜8埋入。n + 型源极区域4和p + 型体区域5从p（n）型沟道区域3延伸到源电极20并与沟槽7交叉。栅极9的上表面位于p沟道区域3的上表面之上。层间绝缘膜10位于沟槽7内，其上表面位于沟槽7的开口下方。源电极20 ，n + 型源区域4和p + 型体区域5分别电连接在一侧沟槽的墙壁7.版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2013089778A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013089778A
公开(公告)日：2013-05-13
申请号：JP2011229183
申请日：2011-10-18
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Denso Corp , 株式会社デンソー
发明人： TAKATANI HIDESHI , MATSUKI HIDEO , SUZUKI MASAHIRO , ISHIKAWA TAKESHI , SOEJIMA SHIGEO , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4236 , H01L21/047 , H01L21/28008 , H01L21/823487 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/41741 , H01L29/42368 , H01L29/66068 , H01L29/66666 , H01L29/7806 , H01L29/7813 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To inhibit a damage of a gate insulation film when breakdown occurs in a semiconductor device using a trench electrode.SOLUTION: A semiconductor manufacturing method comprises: forming source regions of a second conductivity type electrically connected to source electrodes 133, respectively, which are adjacent to a trench 113 penetrating a body region from a surface of a semiconductor substrate 102 to reach a drift region 112; forming a drain electrode 111 on a rear face of the semiconductor substrate; arranging at a bottom of the trench, a specific layer 181 having characteristics forming a depletion layer at a junction with the drift region; covering a top face of the specific layer and side walls of the trench with an insulation layer; forming a gate electrode 122 inside the trench covered with the insulation layer; forming on a part of trench side walls, conductive parts 182 extending along the trench side walls and in a depth direction of the semiconductor substrate; bonding first ends of the conductive parts to the specific layer; and making second ends of the conductive parts reach a surface of the semiconductor substrate and connecting the second ends to the source electrodes.
摘要翻译：要解决的问题：在使用沟槽电极的半导体器件中发生击穿时，抑制栅极绝缘膜的损坏。解决方案：半导体制造方法包括：分别形成与源电极133电连接的第二导电类型的源区，其与从半导体衬底102的表面穿透体区的沟槽113相邻以到达漂移区域112; 在半导体衬底的背面上形成漏电极111; 布置在沟槽的底部，具有在与漂移区域的接合处形成耗尽层的特性的特定层181; 用绝缘层覆盖沟槽的特定层和侧壁的顶面; 在覆盖有绝缘层的沟槽内形成栅电极122; 在沟槽侧壁的一部分上形成导电部分182，沿着沟槽侧壁延伸并沿着半导体衬底的深度方向延伸; 将导电部件的第一端接合到特定层; 并且使导电部件的第二端到达半导体基板的表面，并将第二端连接到源电极。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2012234908A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2012234908A
公开(公告)日：2012-11-29
申请号：JP2011101207
申请日：2011-04-28
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： H01L29/12 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To minimize decline of the isolation voltage and the life of a gate insulating film, by suppressing unevenness of the side surface and the bottom surface of a trench.SOLUTION: A trench 6 is formed so as to have the direction perpendicular to the direction, i.e. the off direction of an SiC semiconductor substrate, as the longitudinal direction. Since a step bunching SB does not traverse the trench 6, formation of unevenness on the side surface and the bottom surface of the trench 6 due to the step bunching SB can be substantially prevented. Consequently, a gate oxide film 8 is formed on the side surface and the bottom surface of the trench 6 having no unevenness, and decline of the isolation voltage and the life of the gate oxide film 8 can be minimized.
摘要翻译：要解决的问题：通过抑制沟槽的侧表面和底表面的不均匀性来最小化隔离电压的下降和栅极绝缘膜的寿命。解决方案：形成沟槽6，使其具有与<11-20>方向垂直的<1-100>方向，即SiC半导体衬底的关闭方向作为纵向方向。由于台阶聚束SB不穿过沟槽6，所以可以基本上防止由于台阶聚束SB而在沟槽6的侧面和底面上形成凹凸。因此，在不具有不均匀性的沟槽6的侧面和底面上形成栅氧化膜8，能够使隔离电压下降和栅极氧化膜8的使用寿命最小化。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2006128507A Insulated-gate semiconductor device and manufacturing method thereof 有权
标题翻译：绝缘栅半导体器件及其制造方法
公开(公告)号：JP2006128507A
公开(公告)日：2006-05-18
申请号：JP2004316912
申请日：2004-10-29
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , MIYAGI KYOSUKE , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/0623 , H01L29/0653 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide an insulated-gate semiconductor device and a manufacturing method thereof wherein high withstand voltage and compactness are made compatible. SOLUTION: In the semiconductor device 100, a gate trench 21 and a p-floating region 51 are formed in a cell area, and a terminating trench 62 and a p-floating region 53 are formed in a terminating area. Further, the inside of the terminating trench 621 among three terminating trenches 62 (terminating trench 621, terminating trench 622, terminating trench 623) has the same structure as the gate trench 21, and the other terminating trenches have a structure filled with an insulator such as silicon oxide etc. Further, the p-floating region 51 is formed by injecting an impurity from the underside of the gate trench 21, and the p-floating region 53 is formed by injecting an impurity from the underside of the terminating trench 62. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种绝缘栅半导体器件及其制造方法，其中高耐受电压和紧凑性被兼容。解决方案：在半导体器件100中，在单元区域中形成栅极沟槽21和p浮动区域51，并且在终止区域中形成端接沟槽62和p浮动区域53。此外，三个端接沟槽62（端接沟槽621，终端沟槽622，终止沟槽623）中的端接沟槽621的内部具有与栅极沟槽21相同的结构，并且其它端接沟槽具有填充有绝缘体的结构作为氧化硅等。此外，通过从栅沟槽21的下侧注入杂质形成p浮置区51，并且通过从终止沟62的下侧注入杂质形成p浮置区53。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005223255A Insulated gate semiconductor apparatus and its manufacturing process 有权
标题翻译：绝缘栅半导体器件及其制造工艺
公开(公告)号：JP2005223255A
公开(公告)日：2005-08-18
申请号：JP2004032001
申请日：2004-02-09
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , MIYAGI KYOSUKE , OKURA YASUTSUGU , TOKURA NORIHITO , KUROYANAGI AKIRA
IPC分类号： H01L21/3065 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/42368 , H01L29/513 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate semiconductor apparatus capable of suppressing device characteristic deterioration due to seam and void arising in a sedimentary insulating layer, and to provide a method for manufacturing the insulated gate semiconductor.
SOLUTION: This semiconductor apparatus is manufactured in the following processes: a gate trench 21 is formed by dry etching; an insulating film 23 with a good coating performance is embedded into the gate trench 21; a part of the insulating film 23 is etched back by dry etching; wet etching is conducted to cope with film damage; a gate oxide film 24 is formed on the wall of the gate trench 21; a cover insulating film 241 with an inadequate coating performance is formed in the gate trench 21, to seal a cuneate channel 233; a gate material 22 is accumulated; finally, the accumulated material 22 is etched so that source and drain electrodes are formed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种能够抑制由沉积绝缘层中产生的接缝和空隙引起的器件特性劣化的绝缘栅半导体器件，并提供一种制造绝缘栅极半导体的方法。解决方案：该半导体装置通过以下工艺制造：通过干蚀刻形成栅沟槽21; 具有良好涂层性能的绝缘膜23被嵌入到栅极沟槽21中; 绝缘膜23的一部分通过干蚀刻被回蚀刻; 进行湿法蚀刻以应对膜损坏; 栅极氧化膜24形成在栅极沟槽21的壁上; 在栅沟槽21中形成具有不良涂层性能的覆盖绝缘膜241，以密封楔形沟槽233; 堆积栅极材料22; 最后，对积聚的材料22进行蚀刻，形成源极和漏极。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2004363498A Power semiconductor device and method for manufacturing same 有权
公开(公告)号：JP2004363498A
公开(公告)日：2004-12-24
申请号：JP2003162866
申请日：2003-06-06
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , OKURA YASUTSUGU , KUROYANAGI AKIRA
IPC分类号： H01L21/336 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/0623 , H01L29/0634 , H01L29/42368 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide an element structure which can realize a MOS FET having a low ON resistance and a high breakdown voltage.
SOLUTION: In the power semiconductor device comprising a gate electrode 11 buried in a groove via a gate insulating film, a p-type depletion region enlargement layer 4 is provided between two n-type drift layers 3 and 5, and the groove is formed to reach the n-type drift layer 3. An n-type converted region the conduction type of which is converted to an n-type is formed in a region in the vicinity of the groove of the p type depletion region enlargement layer, thus forming a carrier path.
COPYRIGHT: (C)2005,JPO&NCIPI

8. 发明专利

JP2004273849A Power semiconductor device and manufacturing method thereof 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：JP2004273849A
公开(公告)日：2004-09-30
申请号：JP2003063897
申请日：2003-03-10
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , TOKURA NORIHITO
IPC分类号： H01L21/336 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236
摘要： PROBLEM TO BE SOLVED: To provide an element structure whereby a MOS FET with a low on-resistance and a high withstand voltage can be realized at a low cost, and to provide a manufacturing method thereof.
SOLUTION: In the power semiconductor device provided with gate electrodes 30 each embedded in a groove via a gate isolation film, the groove has an opening on the surface of semiconductor, and comprises a perpendicular groove extended perpendicularly from the opening, and one or more tilt grooves 10b, 10c extended from the opening in directions different from the perpendicular groove. Source regions 5a, 5b and 5c, 5d on both sides of the tilt grooves 10b, 10c are respectively located adjacent to each other.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以以低成本实现具有低导通电阻和高耐受电压的MOS FET的元件结构，并提供其制造方法。解决方案：在具有通过栅极隔离膜嵌入凹槽中的栅电极30的功率半导体器件中，凹槽在半导体表面上具有开口，并且包括从开口垂直延伸的垂直凹槽，并且一个或更多个倾斜槽10b，10c从开口沿与垂直槽不同的方向延伸。倾斜槽10b，10c两侧的源区域5a，5b，5c，5d分别相邻配置。版权所有（C）2004，JPO＆NCIPI

9. 发明专利

JP2004214542A Vertical power mosfet 有权
公开(公告)号：JP2004214542A
公开(公告)日：2004-07-29
申请号：JP2003002161
申请日：2003-01-08
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , KUROYANAGI AKIRA
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a vertical power MOSFET capable of obtaining its low on-resistance without increasing the thickness of its gate oxide film.
SOLUTION: The vertical power MOSFET has an epitaxial layer 4 so formed on the surface of a substrate 1 having a drain electrode 2 on the rear surface thereof as to form an oxide-film layer 3 on the substrate 1, a body layer 5 provided on the surface of the epitaxial layer 4, source regions 7 provided at a part of the body layer 5, a trench gate 9 provided in a position interposed between the source regions 7 and so joined to the oxide-film layer 3 as not to contact with the substrate 1, and trench drains 11 so provided as to oppose the trench gate 9, as to be repeatedly alternated with the trench gate 9, and as to contact with the substrate 1 by passing through the oxide-film layer 3.
COPYRIGHT: (C)2004,JPO&NCIPI

10. 发明专利

JP2013191734A Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2013191734A
公开(公告)日：2013-09-26
申请号：JP2012057175
申请日：2012-03-14
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Denso Corp , 株式会社デンソー
发明人： TAKATANI HIDESHI , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO , SAKAKIBARA JUN
IPC分类号： H01L29/06 , H01L29/12 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve breakdown strength characteristics of a semiconductor device.SOLUTION: A semiconductor device 100 includes a terminal area 107 that encloses a cell area 105. The terminal area 107 includes termination trenches 161-163, and diffusion regions 181-186. The terminal trenches 161-163 reach a drift region 112 from the surface of a semiconductor substrate 102 by penetrating a body region 141, with an oxide film 171 formed inside it. At each of bottom parts of the termination trenches 161-163, a floating region 151 which is p-type and is enclosed with the drift region 112 is formed. The diffusion regions 181-186 are p-type and are formed in a region on the outer peripheral side of the termination trench 163. A position of lower end parts of the diffusion regions 181-186 is above the position of the floating region 151 while below a lower end part of the body region 141.
摘要翻译：要解决的问题：提高半导体器件的击穿强度特性。解决方案：半导体器件100包括封装单元区域105的端子区域107.端子区域107包括终止沟槽161-163和扩散区域181-186 。端子沟槽161-163通过穿透体区域141而从半导体衬底102的表面到达漂移区域112，其中形成有氧化物膜171。在端接槽161-163的每个底部，形成p型并与漂移区域112包围的浮动区域151。扩散区域181-186是p型的，并且形成在终端沟槽163的外周侧的区域中。扩散区域181-186的下端部分的位置高于浮动区域151的位置，而在身体区域141的下端部分下方。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式