专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2006093459A Trench gate type semiconductor device and its manufacturing method 有权
标题翻译： TRENCH门式半导体器件及其制造方法
公开(公告)号：JP2006093459A
公开(公告)日：2006-04-06
申请号：JP2004278187
申请日：2004-09-24
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L29/78 , H01L21/336 , H01L27/04
CPC分类号： H01L29/0619 , H01L29/0623 , H01L29/0642 , H01L29/407 , H01L29/42368 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813 , H01L29/7815
摘要： PROBLEM TO BE SOLVED: To provide a trench gate type semiconductor device which has a highly precise current sensing function and in which a high breakdown voltage is attained, and to provide a method of manufacturing it. SOLUTION: The semiconductor device 100 includes a main cell 1 and a sense cell 2. The main cell 1 and the sense cell 2 are separated by a separated area 3. The main cell 1 and the sense cell 2 of the semiconductor device 100 become a mechanism which supports a breakdown voltage by P floating regions 51 and 52, in addition to the PN junction of an N - drift region 12 and a P - body region 41. A breakdown voltage maintaining mechanism equivalent to the main cell 1 and the sense cell 2 is provided even in the separated area 3 of the semiconductor device 100. More particularly, the P floating region 53 and its bottom reach the P floating region 53, and the gate trench 81 which contains a gate electrode 84 is provided. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供具有高精度电流感测功能并且其中获得高击穿电压的沟槽栅型半导体器件，并提供其制造方法。解决方案：半导体器件100包括主单元1和感测单元2.主单元1和感测单元2由分离区域3分隔开。半导体器件的主单元1和感测单元2 100成为除P漂移区域12和P - / SP>体区域的PN结以外还支持P浮动区域51和52的击穿电压的机构即使在半导体器件100的分离区域3中也设置有与主单元1和感测单元2相当的击穿电压维持机构。更具体地，P浮动区域53及其底部到达P浮动区域53，并且设置包含栅极电极84的栅极沟槽81。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006093457A Insulated gate type semiconductor device 审中-公开
标题翻译：绝缘栅型半导体器件
公开(公告)号：JP2006093457A
公开(公告)日：2006-04-06
申请号：JP2004278157
申请日：2004-09-24
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L29/78
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0623 , H01L29/0642 , H01L29/1095 , H01L29/42368 , H01L29/7811 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate type semiconductor device which makes a rise in breakdown voltage and reduction in on-stage resistance compatible and which further improves the breakdown voltage and the on-stage resistance. SOLUTION: The semiconductor device 100 includes an N + source region 31, a P + diffusion region 32, an N + drain region 11, a P - body region 41 and an N - drift region 12. Moreover, a gate trench 21 is formed by digging the part by the side of the upper surface of the semiconductor device 100. A P floating region 52 is formed under a gate trench 21. Moreover, a P + diffusion region 32 formed in a high concentration rather than the P - body region 41 is formed. Moreover, a P + diffusion region 32 formed in a higher concentration than the P - body region 41 is formed on the intermediate point between the gate trenches 21 and 21 of the upper surface side. Further, the depth of the P + diffusion region 32 is within a range of 70-100% of the depth of the P - body region 41. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种绝缘栅型半导体器件，其使击穿电压升高并且降低阶段电阻的兼容性，并且进一步提高了击穿电压和导通电阻。解决方案：半导体器件100包括N + SP源极区31，P + SP扩散区32，N 漏区 11，P - / SP体漂移区域12和N - / SP>漂移区域12.此外，栅沟槽21是通过将部分的上表面侧 AP浮动区域52形成在栅极沟槽21的下方。此外，形成为高浓度而不是P - SP体的P + SP扩散区域32 形成区域41。此外，在上部的栅极沟槽21和21之间的中间点上形成有比P 体区域41更高的浓度形成的P + 扩散区域32。表面此外，P + 扩散区域32的深度在P体积区域41的深度的70-100％的范围内。COPYRIGHT：（C）2006，JPO＆NCIPI

3. 发明专利

JP2006128507A Insulated-gate semiconductor device and manufacturing method thereof 有权
标题翻译：绝缘栅半导体器件及其制造方法
公开(公告)号：JP2006128507A
公开(公告)日：2006-05-18
申请号：JP2004316912
申请日：2004-10-29
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , MIYAGI KYOSUKE , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/0623 , H01L29/0653 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide an insulated-gate semiconductor device and a manufacturing method thereof wherein high withstand voltage and compactness are made compatible. SOLUTION: In the semiconductor device 100, a gate trench 21 and a p-floating region 51 are formed in a cell area, and a terminating trench 62 and a p-floating region 53 are formed in a terminating area. Further, the inside of the terminating trench 621 among three terminating trenches 62 (terminating trench 621, terminating trench 622, terminating trench 623) has the same structure as the gate trench 21, and the other terminating trenches have a structure filled with an insulator such as silicon oxide etc. Further, the p-floating region 51 is formed by injecting an impurity from the underside of the gate trench 21, and the p-floating region 53 is formed by injecting an impurity from the underside of the terminating trench 62. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种绝缘栅半导体器件及其制造方法，其中高耐受电压和紧凑性被兼容。解决方案：在半导体器件100中，在单元区域中形成栅极沟槽21和p浮动区域51，并且在终止区域中形成端接沟槽62和p浮动区域53。此外，三个端接沟槽62（端接沟槽621，终端沟槽622，终止沟槽623）中的端接沟槽621的内部具有与栅极沟槽21相同的结构，并且其它端接沟槽具有填充有绝缘体的结构作为氧化硅等。此外，通过从栅沟槽21的下侧注入杂质形成p浮置区51，并且通过从终止沟62的下侧注入杂质形成p浮置区53。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005223255A Insulated gate semiconductor apparatus and its manufacturing process 有权
标题翻译：绝缘栅半导体器件及其制造工艺
公开(公告)号：JP2005223255A
公开(公告)日：2005-08-18
申请号：JP2004032001
申请日：2004-02-09
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , MIYAGI KYOSUKE , OKURA YASUTSUGU , TOKURA NORIHITO , KUROYANAGI AKIRA
IPC分类号： H01L21/3065 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/42368 , H01L29/513 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate semiconductor apparatus capable of suppressing device characteristic deterioration due to seam and void arising in a sedimentary insulating layer, and to provide a method for manufacturing the insulated gate semiconductor.
SOLUTION: This semiconductor apparatus is manufactured in the following processes: a gate trench 21 is formed by dry etching; an insulating film 23 with a good coating performance is embedded into the gate trench 21; a part of the insulating film 23 is etched back by dry etching; wet etching is conducted to cope with film damage; a gate oxide film 24 is formed on the wall of the gate trench 21; a cover insulating film 241 with an inadequate coating performance is formed in the gate trench 21, to seal a cuneate channel 233; a gate material 22 is accumulated; finally, the accumulated material 22 is etched so that source and drain electrodes are formed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种能够抑制由沉积绝缘层中产生的接缝和空隙引起的器件特性劣化的绝缘栅半导体器件，并提供一种制造绝缘栅极半导体的方法。解决方案：该半导体装置通过以下工艺制造：通过干蚀刻形成栅沟槽21; 具有良好涂层性能的绝缘膜23被嵌入到栅极沟槽21中; 绝缘膜23的一部分通过干蚀刻被回蚀刻; 进行湿法蚀刻以应对膜损坏; 栅极氧化膜24形成在栅极沟槽21的壁上; 在栅沟槽21中形成具有不良涂层性能的覆盖绝缘膜241，以密封楔形沟槽233; 堆积栅极材料22; 最后，对积聚的材料22进行蚀刻，形成源极和漏极。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004273849A Power semiconductor device and manufacturing method thereof 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：JP2004273849A
公开(公告)日：2004-09-30
申请号：JP2003063897
申请日：2003-03-10
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , TOKURA NORIHITO
IPC分类号： H01L21/336 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236
摘要： PROBLEM TO BE SOLVED: To provide an element structure whereby a MOS FET with a low on-resistance and a high withstand voltage can be realized at a low cost, and to provide a manufacturing method thereof.
SOLUTION: In the power semiconductor device provided with gate electrodes 30 each embedded in a groove via a gate isolation film, the groove has an opening on the surface of semiconductor, and comprises a perpendicular groove extended perpendicularly from the opening, and one or more tilt grooves 10b, 10c extended from the opening in directions different from the perpendicular groove. Source regions 5a, 5b and 5c, 5d on both sides of the tilt grooves 10b, 10c are respectively located adjacent to each other.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以以低成本实现具有低导通电阻和高耐受电压的MOS FET的元件结构，并提供其制造方法。解决方案：在具有通过栅极隔离膜嵌入凹槽中的栅电极30的功率半导体器件中，凹槽在半导体表面上具有开口，并且包括从开口垂直延伸的垂直凹槽，并且一个或更多个倾斜槽10b，10c从开口沿与垂直槽不同的方向延伸。倾斜槽10b，10c两侧的源区域5a，5b，5c，5d分别相邻配置。版权所有（C）2004，JPO＆NCIPI

6. 发明专利

JP2006210392A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006210392A
公开(公告)日：2006-08-10
申请号：JP2005016584
申请日：2005-01-25
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L27/06 , H01L21/8234 , H01L29/47 , H01L29/872
CPC分类号： H01L29/0623 , H01L29/0649 , H01L29/1608 , H01L29/20 , H01L29/2003 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/66143 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7806 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a Schottky barrier diode and a power MOS transistor are formed on the same substrate and which suppresses locally concentrated generation of heat, has high pressure resistance and low on-resistance, and can be easily manufactured; and to provide a manufacturing method thereof.
SOLUTION: The semiconductor device 200 is a trench gate type semiconductor device in which the Schottky barrier diode and the power MOS are formed on the same substrate, wherein a Schottky range and a MOS range are alternately arranged using a trench gate 21 as a boundary. Further, three regions (N
- drift region 12sm, an N
-- drift region 12s and an N drift region 12m) having different density are arranged in an N
- drift region 12. In concrete, the region 12s positioned in the Schottky region is a low density region, and the region 12m positioned in the MOS region is a high density region.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种半导体器件，其中在同一衬底上形成肖特基势垒二极管和功率MOS晶体管并且抑制局部集中的发热，具有高耐压性和低导通电阻，以及可以容易地制造; 并提供其制造方法。解决方案：半导体器件200是在同一衬底上形成肖特基势垒二极管和功率MOS的沟槽栅型半导体器件，其中肖特基范围和MOS范围使用沟槽栅极21交替布置为边界此外，具有不同密度的三个区域（N - / SP>漂移区域12sm，N - SP漂移区域12s和N漂移区域12m）排列在N 具体而言，位于肖特基区域的区域12s为低密度区域，位于MOS区域的区域12m为高密度区域。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2006202940A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006202940A
公开(公告)日：2006-08-03
申请号：JP2005012365
申请日：2005-01-20
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , MIYAGI KYOSUKE , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method wherein on-resistance is reduced by a simplified manufacturing process and it has a floating region within a drift region. SOLUTION: The semiconductor device 100 has high withstand voltage with the aid of a p-floating region 51 embedded in an N - drift region 12. The p-floating region 51 is provided with a pitch where depletion regions extending from the p-floating region 51 are connected with each other just before the device is broken down. This allows the pitch of the P floating region 51 to be widened to reduce a drift resistance component. The semiconductor device 100 includes a gate trench 25 having a shallow depth than a gate trench 21 between the gate trenches 21, 21 used for the formation of the p-floating region 51. Consequently, the semiconductor device 100 has high channel density to result in a small channel resistance component. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件及其制造方法，其中通过简化的制造工艺降低导通电阻并且其在漂移区域内具有浮动区域。解决方案：借助于嵌入在N漂移区12中的p浮置区51，半导体器件100具有高耐受电压.p浮置区51具有间距其中从p浮动区域51延伸的耗尽区域在器件分解之前彼此连接。这允许P浮动区域51的间距变宽以减小漂移电阻分量。半导体器件100包括栅极沟槽25，栅极沟槽25具有比用于形成p浮置区域51的栅极沟槽21,21之间的栅极沟槽21浅的深度。因此，半导体器件100具有高沟道密度，导致小通道电阻分量。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2006013017A Manufacture of insulated gate type semiconductor device 有权
标题翻译：绝缘栅型半导体器件的制造
公开(公告)号：JP2006013017A
公开(公告)日：2006-01-12
申请号：JP2004185773
申请日：2004-06-24
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： MIYAGI KYOSUKE , IKEDA TOMOHARU , TAKATANI HIDESHI , OKURA YASUTSUGU , TOKURA NORIHITO , KUROYANAGI AKIRA
IPC分类号： H01L29/78 , H01L21/316 , H01L21/336
CPC分类号： H01L29/0623 , H01L29/0649 , H01L29/1095 , H01L29/42368 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an insulated gate type semiconductor device in which the void in a deposited insulation layer is eliminated to suppress degradation of element characteristics due to the effect of the void. SOLUTION: After a gate trench 21 and a terminal trench 61 are formed, the area where no impurity is doped, in other words a non-doped insulating film, is embedded in each trench. Then, a semiconductor substrate where the insulating film is formed is subjected to annealing process in an oxidizing atmosphere. Thus, a thermally-oxidized film 83 is formed along the wall surface of gate trench 21, resulting in eliminating a void in a deposited insulation layer 23. Then a part of the deposited insulation layer 23 is etched back, and the space provided by the etching-back is packed with a gate material. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造绝缘栅型半导体器件的方法，其中消除了沉积绝缘层中的空隙，以抑制由于空隙的影响导致的元件特性的劣化。解决方案：在形成栅极沟槽21和端子沟槽61之后，在每个沟槽中嵌入不掺杂杂质的区域，换句话说是非掺杂绝缘膜。然后，在氧化气氛中对形成绝缘膜的半导体衬底进行退火处理。因此，沿着栅极沟槽21的壁面形成热氧化膜83，从而消除了沉积的绝缘层23中的空隙。然后，沉积的绝缘层23的一部分被回蚀刻，并且由蚀刻回填装有栅极材料。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005286042A Insulated gate type semiconductor device and its manufacturing method 有权
标题翻译：绝缘栅型半导体器件及其制造方法
公开(公告)号：JP2005286042A
公开(公告)日：2005-10-13
申请号：JP2004096785
申请日：2004-03-29
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , MIYAGI KYOSUKE , OKURA YASUTSUGU , TOKURA NORIHITO
IPC分类号： H01L29/78
CPC分类号： H01L29/0623 , H01L29/0661 , H01L29/0696 , H01L29/42368 , H01L29/7811 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate type semiconductor device which can certainly raise a breakdown voltage and reduce an on-state resistance and can be simply manufactured, and to provide a method of manufacturing the same.
SOLUTION: The semiconductor device 100 comprises an n
+ -type source region 31, an n
+ -type drain region 11, a p
- -type body region 41 and an n
- -type drift region 12. Moreover, a gate trench 21 which penetrates the p
- -type body region 41, a breakdown holding trench 27, and a breakdown voltage holding trench 27; and a termination trench 62 are provided, respectively. And, under the each trench, P floating regions 51, 57 and 53 are formed, respectively. The inner diameter L1 of the gate trench 21 of the minimum diameter is wider than the interval L2 between the gate trenches 21 and 21 of a cell area. Moreover, the interval L3 between the gate trench 21 of the minimum diameter and the breakdown holding trench 27 is narrower than the interval L2 between the gate trenches 21 and 21 of the cell area.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以提高击穿电压并降低导通电阻并且可以简单制造的绝缘栅型半导体器件，并提供其制造方法。解决方案：半导体器件100包括n + SP + + SP型 - 源极区域31，n + SP + + / SP - 型漏极区域11， >型体区41和n - / SP>型漂移区12.此外，穿过p 型体区41的栅极沟槽21，击穿保持沟槽27和击穿电压保持沟槽27; 并且分别设置有终端沟槽62。并且，在每个沟槽下分别形成P个浮动区域51,57和53。栅极沟槽21的最小直径的内径L1比单元区域的栅极沟槽21和21之间的间隔L2宽。此外，最小直径的栅极沟槽21与击穿保持沟槽27之间的间隔L3比单元区域的栅极沟槽21和21之间的间隔L2窄。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2005252203A Insulated gate type semiconductor device and its manufacturing method 审中-公开
标题翻译：绝缘栅型半导体器件及其制造方法
公开(公告)号：JP2005252203A
公开(公告)日：2005-09-15
申请号：JP2004064696
申请日：2004-03-08
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , SASAKI SHIGEMI , OKURA YASUTSUGU , TOKURA NORIHITO , KUROYANAGI AKIRA
IPC分类号： H01L29/423 , H01L21/336 , H01L29/12 , H01L29/41 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/511 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate type semiconductor device in which a deterioration of breakdown voltage influenced by seam is suppressed, and to provide its manufacturing method.
SOLUTION: The method comprises the steps of: forming a gate trench 21 by dry etching; embedding an oxide film 23 with respect to the gate trench 21; depositing so that an inside of the gate trench 21 may not be completely filled but some clearance may be left; embedding a nitride film 231 with respect to the clearance; performing an etch back of the nitride film 231 and the oxide film 23 by performing wet etching in such a state that the nitride film 231 is left inside the gate trench 21 because it is hardly etched; forming an oxide film 24 in a surface of a wall of the gate trench 21; depositing a gate material 22; and forming a source electrode and a drain electrode by etching the deposited gate material 22.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种绝缘栅型半导体器件，其中抑制了受接缝影响的击穿电压的劣化，并提供其制造方法。解决方案：该方法包括以下步骤：通过干蚀刻形成栅极沟槽21; 相对于栅沟槽21嵌入氧化膜23; 沉积，使得栅极沟槽21的内部可能不被完全填充，但可能留下一些间隙; 相对于间隙嵌入氮化物膜231; 在氮化膜231由于几乎不被蚀刻而留在栅极沟槽21内的状态下进行湿式蚀刻来进行氮化膜231和氧化物膜23的蚀刻; 在栅极沟槽21的壁表面形成氧化物膜24; 沉积栅极材料22; 并通过蚀刻沉积的栅极材料22形成源电极和漏电极。版权所有（C）2005，JPO＆NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式