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1. 发明专利

JP2014110305A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2014110305A
公开(公告)日：2014-06-12
申请号：JP2012263471
申请日：2012-11-30
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Denso Corp , 株式会社デンソー
发明人： TSUJIMURA MASATOSHI , FUJIWARA HIROKAZU , MORINO TOMOO , SOEJIMA SHIGEMASA
IPC分类号： H01L21/324 , H01L21/265
CPC分类号： H01L21/046 , H01L21/67303 , H01L29/1608
摘要： PROBLEM TO BE SOLVED: To provide an art to inhibit roughening of a wafer surface caused by Si atom desorption from a surface of a silicon carbide wafer in a heat treatment process of a semiconductor device and increase production efficiency of the semiconductor device.SOLUTION: A semiconductor device manufacturing method disclosed in the present embodiment comprises an arrangement process and a heat treatment process. In the arrangement process, a plurality of silicon carbide wafers 10 each including a first surface 16 and a second surface 18 which is a rear face of the first surface in a manner such that the centers of the silicon carbide wafers 10 are coaxially located and the first surface 16 and the second surface 18 of the adjacent silicon carbide wafers are opposite to each other and separated in parallel with each other. In the heat treatment process, the plurality of silicon carbide wafers 10 arranged in the arrangement process are heated in a manner such that a temperature of the first surface 16 of each silicon carbide wafer becomes higher than that of the second surface 18 and a temperature of the second surface 18 of one silicon carbide wafer 10 between the adjacent silicon carbide wafers 10 becomes higher than that of the first surface 16 of the other silicon carbide wafer which is opposite to the second surface 18.
摘要翻译：要解决的问题：提供一种在半导体器件的热处理工艺中抑制由硅化物晶片的表面Si原子解吸引起的晶片表面粗糙化的技术，并提高半导体器件的生产效率。解决方案：A 本实施例中公开的半导体器件制造方法包括布置处理和热处理工艺。在排列过程中，多个碳化硅晶片10各自包括第一表面16和第二表面18，第二表面18是第一表面的后表面，其方式使得碳化硅晶片10的中心位于同轴位置，并且相邻的碳化硅晶片的第一表面16和第二表面18彼此相对并且彼此平行地分离。在热处理工序中，以配置方式配置的多个碳化硅晶片10的加热方式使得每个碳化硅晶片的第一表面16的温度变得高于第二表面18的温度，在相邻碳化硅晶片10之间的一个碳化硅晶片10的第二表面18变得高于与第二表面18相对的另一个碳化硅晶片的第一表面16的第二表面18。

2. 发明专利

JP2013258369A Silicon carbide semiconductor device and manufacturing method of the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2013258369A
公开(公告)日：2013-12-26
申请号：JP2012134917
申请日：2012-06-14
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社
发明人： TAKEUCHI YUICHI , SENDA KAZUMI , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO
IPC分类号： H01L21/336 , H01L29/06 , H01L29/12 , H01L29/78
CPC分类号： H01L29/66068 , H01L21/02529 , H01L21/0455 , H01L21/0475 , H01L21/049 , H01L21/3065 , H01L29/045 , H01L29/0619 , H01L29/0623 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To enable manufacturing of a SiC semiconductor device which can support a high withstanding voltage and a high switching speed at the same time regardless of ion implantation.SOLUTION: A silicon carbide semiconductor device manufacturing method comprises: forming a p-type layer 31 in a trench 6 by epitaxial growth; and subsequently forming a p-type SiC layer 7 by leaving the p-type layer 31 only at a bottom and both tips of the trench 6 by hydrogen etching. More specifically, a part of the p-type layer 31, which is formed on lateral faces of the trench 6 is removed. By doing this, the p-type SiC layer 7 can be formed regardless of oblique ion implantation. Accordingly, because additional oblique ion implantation is not necessary, complicated manufacturing processes such as transfer to an ion implantation device can be inhibited thereby to reduce manufacturing cost. Further, because there is no defect damage due to ion implantation, a drain leakage can be inhibited and the p-type SiC layer 7 can be reliably prevented from being left on the lateral faces of the trench 6.
摘要翻译：要解决的问题：能够制造能够同时支持高耐压和高开关速度的SiC半导体器件，而不管离子注入如何。解决方案：一种碳化硅半导体器件的制造方法包括：形成p型通过外延生长在沟槽6中的层31; 然后通过氢蚀刻在沟槽6的底部和两个尖端处留下p型层31而形成p型SiC层7。更具体地，去除形成在沟槽6的侧面上的p型层31的一部分。通过这样做，可以形成p型SiC层7，而不管倾斜离子注入。因此，由于不需要额外的斜离子注入，因此可以抑制诸如转移到离子注入装置的复杂的制造工艺，从而降低制造成本。此外，由于没有因离子注入导致的缺陷损伤，所以可以抑制漏极泄漏，并且可以可靠地防止p型SiC层7留在沟槽6的侧面上。

3. 发明专利

JP2013197143A Semiconductor device and semiconductor device manufacturing method 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：JP2013197143A
公开(公告)日：2013-09-30
申请号：JP2012059861
申请日：2012-03-16
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Denso Corp , 株式会社デンソー
发明人： SUGIMOTO MASAHIRO , SOEJIMA SHIGEMASA , YAMAMOTO KENSAKU
IPC分类号： H01L29/78 , H01L21/336 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having high voltage resistance.SOLUTION: A semiconductor device comprises: a semiconductor substrate on which trenches are formed on a surface; an insulation film covering an inner surface of each trench; and an electrode arranged in each trench. In a cross section which traverses the trench, a curve which links a wall surface and a bottom of the trench is steeper than a curve which links a wall surface and a bottom of the electrode. Accordingly, an electric field applied to the insulation film near a corner of the electrode is relaxed and the insulation film near the corner of the electrode is formed thicker.
摘要翻译：要解决的问题：提供一种具有高耐电压性的半导体器件。解决方案：一种半导体器件包括：半导体衬底，其上在其上形成沟槽; 覆盖每个沟槽的内表面的绝缘膜; 以及布置在每个沟槽中的电极。在穿过沟槽的横截面中，连接壁表面和沟槽底部的曲线比连接电极的壁表面和底部的曲线更陡。因此，施加到电极角附近的绝缘膜的电场被松弛，并且电极角附近的绝缘膜形成得较厚。

4. 发明专利

JP2012234908A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2012234908A
公开(公告)日：2012-11-29
申请号：JP2011101207
申请日：2011-04-28
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： H01L29/12 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To minimize decline of the isolation voltage and the life of a gate insulating film, by suppressing unevenness of the side surface and the bottom surface of a trench.SOLUTION: A trench 6 is formed so as to have the direction perpendicular to the direction, i.e. the off direction of an SiC semiconductor substrate, as the longitudinal direction. Since a step bunching SB does not traverse the trench 6, formation of unevenness on the side surface and the bottom surface of the trench 6 due to the step bunching SB can be substantially prevented. Consequently, a gate oxide film 8 is formed on the side surface and the bottom surface of the trench 6 having no unevenness, and decline of the isolation voltage and the life of the gate oxide film 8 can be minimized.
摘要翻译：要解决的问题：通过抑制沟槽的侧表面和底表面的不均匀性来最小化隔离电压的下降和栅极绝缘膜的寿命。解决方案：形成沟槽6，使其具有与<11-20>方向垂直的<1-100>方向，即SiC半导体衬底的关闭方向作为纵向方向。由于台阶聚束SB不穿过沟槽6，所以可以基本上防止由于台阶聚束SB而在沟槽6的侧面和底面上形成凹凸。因此，在不具有不均匀性的沟槽6的侧面和底面上形成栅氧化膜8，能够使隔离电压下降和栅极氧化膜8的使用寿命最小化。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2012069798A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012069798A
公开(公告)日：2012-04-05
申请号：JP2010214245
申请日：2010-09-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： FUJIWARA HIROKAZU , KONISHI MASAKI , MORIMOTO ATSUSHI , KATSUNO TAKASHI , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , KAWAI JUN , ENDO TAKESHI , YAMAMOTO TAKEO
IPC分类号： H01L21/28
CPC分类号： H01L29/872 , H01L23/3192 , H01L2224/05567 , H01L2224/06181 , H01L2924/00014 , H01L2924/12032 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of forming an excellent ohmic electrode in an atmosphere other than a non-oxidative atmosphere.SOLUTION: A method of manufacturing a semiconductor device having an ohmic electrode comprises the steps of: forming a metal layer 30e on a semiconductor substrate 50; forming a transmission film 30f on the metal layer 30e; heating the metal layer 30e by irradiating the metal layer 30e with an electromagnetic wave through the transmission film 30f; and removing the transmission film 30f.
摘要翻译：解决的问题：提供能够在非氧化性气氛以外的气氛中形成优异的欧姆电极的技术。解决方案：制造具有欧姆电极的半导体器件的方法包括以下步骤：在半导体衬底50上形成金属层30e; 在金属层30e上形成透射膜30f; 通过透过薄膜30f用电磁波照射金属层30e来加热金属层30e; 并移除透射膜30f。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2011119585A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011119585A
公开(公告)日：2011-06-16
申请号：JP2009277547
申请日：2009-12-07
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： FUJIWARA HIROKAZU , KONISHI MASAKI , KATSUNO TAKASHI , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , YAMAMOTO TAKEO , ENDO TAKESHI
IPC分类号： H01L29/47 , H01L21/28 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To secure Schottky junction between a surface electrode and a semiconductor substrate and ohmic junction between a back electrode and the semiconductor substrate, and to simplify manufacturing processes in a method of manufacturing the semiconductor device from a semiconductor wafer made of silicon carbide. SOLUTION: After a surface Mo electrode is formed on the surface of the semiconductor wafer, the back Ni-based electrode is formed on the back of the semiconductor wafer, and the formed surface Mo electrode and back Ni-based electrode are simultaneously subjected to sintering processing. The surface Mo electrode can secure the Schottky junction with the semiconductor substrate even when subjected to the sintering processing at 900°C or higher. The surface electrode and back electrode can be simultaneously subjected to the sintering processing at high temperature (for example, 900°C or above) needed for the back Ni-based electrode to have the ohmic junction with the semiconductor substrate, so the manufacturing processes can be simplified. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了确保表面电极和半导体衬底之间的肖特基结以及背电极和半导体衬底之间的欧姆结，并且为了简化从半导体晶片制造半导体器件的方法中的制造工艺的碳化硅。解决方案：在半导体晶片的表面上形成表面Mo电极之后，在半导体晶片的背面形成背面的Ni基电极，并且形成的表面Mo电极和背面的Ni基电极同时进行烧结处理。即使在900℃以上进行烧结处理，表面Mo电极也可以固定与半导体基板的肖特基结。表面电极和背面电极可以在背面Ni基电极所需的高温（例如900℃以上）下同时进行烧结处理，从而与半导体衬底形成欧姆结，因此制造工艺可以被简化。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2011100948A Semiconductor device, and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011100948A
公开(公告)日：2011-05-19
申请号：JP2009256438
申请日：2009-11-09
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： WATANABE YUKIHIKO , KATSUNO TAKASHI , SOEJIMA SHIGEMASA , YAMAMOTO TAKEO , ENDO TAKESHI , FUJIWARA HIROKAZU , KONISHI MASAKI
IPC分类号： H01L29/47 , H01L29/861 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To decrease a heat damage caused by annealing when the annealing is performed to a back electrode.
SOLUTION: A semiconductor device includes: a silicon carbide substrate 10 where a vertical short key diode is formed; an anode electrode 20 that is provided on a front surface of the silicon carbide substrate 10; a cathode electrode 50 that is provided on a back surface of the silicon carbide substrate 10; and a conductive adiabatic region 40 that is provided between the silicon carbide substrate 10 and the cathode electrode 50. The adiabatic region 40 has heat conductivity smaller than that of a semiconductor material of the silicon carbide substrate 10.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：当对后电极进行退火时，减少由退火引起的热损伤。解决方案：半导体器件包括：形成垂直短路二极管的碳化硅衬底10; 设置在碳化硅衬底10的前表面上的阳极电极20; 设置在碳化硅衬底10的背面上的阴极50; 以及设置在碳化硅衬底10和阴极电极50之间的导电绝热区域40.绝热区域40的导热系数小于碳化硅衬底10的半导体材料的热导率。（C） 2011年，JPO＆INPIT

8. 发明专利

JP2014236120A 半導体装置及びその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014236120A
公开(公告)日：2014-12-15
申请号：JP2013116937
申请日：2013-06-03
申请人：トヨタ自動車株式会社 , Toyota Motor Corp , 株式会社デンソー , Denso Corp
发明人： ISHIMABUSE HISASHI , MIMURA TOMOHIRO , SOEJIMA SHIGEMASA
IPC分类号： H01L29/78 , H01L21/265 , H01L21/28 , H01L21/329 , H01L21/336 , H01L29/12 , H01L29/47 , H01L29/872
CPC分类号： H01L29/1608 , H01L21/046 , H01L21/0465 , H01L21/0495 , H01L29/0619 , H01L29/6606 , H01L29/7802 , H01L29/78642 , H01L29/861 , H01L29/872
摘要：【課題】不純物濃度が比較的低い領域における不純物のチャネリングを抑制する技術を提供する。【解決手段】半導体基板準備工程では、SiCを材料としており、一方の表面に第1導電型の第1半導体領域が形成されている半導体基板を準備する。第2半導体領域形成工程では、半導体基板の一方の表面から第1半導体領域に注入深さを変えながら多段階のイオン注入によって第2導電型の不純物を注入して第2半導体領域を形成する。第2半導体領域形成工程では、多段階のイオン注入において注入エネルギーが最大となるときの不純物のドーズ量が、注入エネルギーが最大でないときの不純物のドーズ量よりも少ない。【選択図】図4
摘要翻译：要解决的问题：提供一种抑制杂质浓度相对较低的区域中的杂质通道的技术。解决方案：在半导体衬底制备步骤中，使用SiC作为材料并具有第一半导体区域的半导体衬底的第一导电类型，形成在一个表面上。在第二半导体区域形成步骤中，在改变植入深度的同时，通过从半导体衬底的一个表面向第一半导体区域注入第二导电类型的杂质，形成第二半导体区域。在第二半导体区域形成步骤中，当多次离子注入中的注入能量最大时的杂质用量小于当注入能量不是最大时杂质的剂量。

9. 发明专利

JP2013214661A Silicon carbide semiconductor device and manufacturing method of the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2013214661A
公开(公告)日：2013-10-17
申请号：JP2012084913
申请日：2012-04-03
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社
发明人： MATSUKI HIDEO , MORIMOTO JUN , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To need not separately perform a process of forming a connection layer for connecting a field relaxation layer on a bottom of a trench and a source electrode.SOLUTION: A silicon carbide semiconductor device manufacturing method comprises: forming one tip surface of a trench 6 to be a plane perpendicular to an off direction, in other words, a plane inclined with respect to a substrate surface, and forming a field relaxation layer 7 by ion implantation from a vertical direction of the substrate. By doing this, a bottom p type layer 7a can be formed at a bottom of the trench 6 and the ion is implanted into the plane inclined with respect to the substrate surface and a tip p type layer 7b can be formed at the same time. Accordingly, the tip p type layer 7b which serves as a connection layer for connecting the bottom p type layer 7a with a source electrode 11 via a p type base region 3 and a ptype contact layer 5 can be formed at the same time. As a result, a process of forming the tip p type layer 7b needs not be performed separately and complicated ion implantation such as oblique ion implantation needs not be performed.
摘要翻译：要解决的问题：不需要单独地执行形成用于连接沟槽底部和源电极上的场弛豫层的连接层的处理。解决方案：一种碳化硅半导体器件制造方法包括：形成一个尖端表面作为垂直于关闭方向的平面的沟槽6，换言之，相对于衬底表面倾斜的平面，以及通过离子注入从衬底的垂直方向形成场弛豫层7。通过这样做，可以在沟槽6的底部形成底部p型层7a，并且将离子注入到相对于衬底表面倾斜的平面中，并且可以同时形成尖端p型层7b。因此，可以同时形成用作通过p型基极区域3和p型接触层5连接底部p型层7a与源极电极11的连接层的尖端p型层7b。结果，不需要单独进行形成尖端p型层7b的工序，不需要复杂的离子注入，例如斜离子注入。

10. 发明专利

JP2013137228A Temperature detection element 有权
标题翻译：温度检测元件
公开(公告)号：JP2013137228A
公开(公告)日：2013-07-11
申请号：JP2011288041
申请日：2011-12-28
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Denso Corp , 株式会社デンソー
发明人： SOENO AKITAKA , YAMAMOTO TOSHIMASA , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA
IPC分类号： G01K7/16
摘要： PROBLEM TO BE SOLVED: To provide a temperature detection element that uses a semiconductor and is capable of detecting high temperature.SOLUTION: A temperature detection element includes a SiC substrate. A dope region where two or more kinds of impurities having the same conductivity type and different activation energy are doped is formed on the SiC substrate. On the surface of the SiC substrate, two electrodes to be in electrical conduction with the dope region are formed. The action of two or more kinds of impurities enables detection of temperature in a wider temperature range.
摘要翻译：要解决的问题：提供使用半导体并能够检测高温的温度检测元件。解决方案：温度检测元件包括SiC衬底。在SiC衬底上形成掺杂有相同导电类型和不同活化能的两种或更多种杂质的掺杂区域。在SiC衬底的表面上，形成与掺杂区域导通的两个电极。两种或更多种杂质的作用使得能够在更宽的温度范围内检测温度。

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