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1. 发明专利

JP2006210392A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006210392A
公开(公告)日：2006-08-10
申请号：JP2005016584
申请日：2005-01-25
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L27/06 , H01L21/8234 , H01L29/47 , H01L29/872
CPC分类号： H01L29/0623 , H01L29/0649 , H01L29/1608 , H01L29/20 , H01L29/2003 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/66143 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7806 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a Schottky barrier diode and a power MOS transistor are formed on the same substrate and which suppresses locally concentrated generation of heat, has high pressure resistance and low on-resistance, and can be easily manufactured; and to provide a manufacturing method thereof.
SOLUTION: The semiconductor device 200 is a trench gate type semiconductor device in which the Schottky barrier diode and the power MOS are formed on the same substrate, wherein a Schottky range and a MOS range are alternately arranged using a trench gate 21 as a boundary. Further, three regions (N
- drift region 12sm, an N
-- drift region 12s and an N drift region 12m) having different density are arranged in an N
- drift region 12. In concrete, the region 12s positioned in the Schottky region is a low density region, and the region 12m positioned in the MOS region is a high density region.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种半导体器件，其中在同一衬底上形成肖特基势垒二极管和功率MOS晶体管并且抑制局部集中的发热，具有高耐压性和低导通电阻，以及可以容易地制造; 并提供其制造方法。解决方案：半导体器件200是在同一衬底上形成肖特基势垒二极管和功率MOS的沟槽栅型半导体器件，其中肖特基范围和MOS范围使用沟槽栅极21交替布置为边界此外，具有不同密度的三个区域（N - / SP>漂移区域12sm，N - SP漂移区域12s和N漂移区域12m）排列在N 具体而言，位于肖特基区域的区域12s为低密度区域，位于MOS区域的区域12m为高密度区域。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006202940A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006202940A
公开(公告)日：2006-08-03
申请号：JP2005012365
申请日：2005-01-20
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , MIYAGI KYOSUKE , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method wherein on-resistance is reduced by a simplified manufacturing process and it has a floating region within a drift region. SOLUTION: The semiconductor device 100 has high withstand voltage with the aid of a p-floating region 51 embedded in an N - drift region 12. The p-floating region 51 is provided with a pitch where depletion regions extending from the p-floating region 51 are connected with each other just before the device is broken down. This allows the pitch of the P floating region 51 to be widened to reduce a drift resistance component. The semiconductor device 100 includes a gate trench 25 having a shallow depth than a gate trench 21 between the gate trenches 21, 21 used for the formation of the p-floating region 51. Consequently, the semiconductor device 100 has high channel density to result in a small channel resistance component. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件及其制造方法，其中通过简化的制造工艺降低导通电阻并且其在漂移区域内具有浮动区域。解决方案：借助于嵌入在N漂移区12中的p浮置区51，半导体器件100具有高耐受电压.p浮置区51具有间距其中从p浮动区域51延伸的耗尽区域在器件分解之前彼此连接。这允许P浮动区域51的间距变宽以减小漂移电阻分量。半导体器件100包括栅极沟槽25，栅极沟槽25具有比用于形成p浮置区域51的栅极沟槽21,21之间的栅极沟槽21浅的深度。因此，半导体器件100具有高沟道密度，导致小通道电阻分量。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006013017A Manufacture of insulated gate type semiconductor device 有权
标题翻译：绝缘栅型半导体器件的制造
公开(公告)号：JP2006013017A
公开(公告)日：2006-01-12
申请号：JP2004185773
申请日：2004-06-24
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： MIYAGI KYOSUKE , IKEDA TOMOHARU , TAKATANI HIDESHI , OKURA YASUTSUGU , TOKURA NORIHITO , KUROYANAGI AKIRA
IPC分类号： H01L29/78 , H01L21/316 , H01L21/336
CPC分类号： H01L29/0623 , H01L29/0649 , H01L29/1095 , H01L29/42368 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an insulated gate type semiconductor device in which the void in a deposited insulation layer is eliminated to suppress degradation of element characteristics due to the effect of the void. SOLUTION: After a gate trench 21 and a terminal trench 61 are formed, the area where no impurity is doped, in other words a non-doped insulating film, is embedded in each trench. Then, a semiconductor substrate where the insulating film is formed is subjected to annealing process in an oxidizing atmosphere. Thus, a thermally-oxidized film 83 is formed along the wall surface of gate trench 21, resulting in eliminating a void in a deposited insulation layer 23. Then a part of the deposited insulation layer 23 is etched back, and the space provided by the etching-back is packed with a gate material. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造绝缘栅型半导体器件的方法，其中消除了沉积绝缘层中的空隙，以抑制由于空隙的影响导致的元件特性的劣化。解决方案：在形成栅极沟槽21和端子沟槽61之后，在每个沟槽中嵌入不掺杂杂质的区域，换句话说是非掺杂绝缘膜。然后，在氧化气氛中对形成绝缘膜的半导体衬底进行退火处理。因此，沿着栅极沟槽21的壁面形成热氧化膜83，从而消除了沉积的绝缘层23中的空隙。然后，沉积的绝缘层23的一部分被回蚀刻，并且由蚀刻回填装有栅极材料。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005252203A Insulated gate type semiconductor device and its manufacturing method 审中-公开
标题翻译：绝缘栅型半导体器件及其制造方法
公开(公告)号：JP2005252203A
公开(公告)日：2005-09-15
申请号：JP2004064696
申请日：2004-03-08
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , SASAKI SHIGEMI , OKURA YASUTSUGU , TOKURA NORIHITO , KUROYANAGI AKIRA
IPC分类号： H01L29/423 , H01L21/336 , H01L29/12 , H01L29/41 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/511 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate type semiconductor device in which a deterioration of breakdown voltage influenced by seam is suppressed, and to provide its manufacturing method.
SOLUTION: The method comprises the steps of: forming a gate trench 21 by dry etching; embedding an oxide film 23 with respect to the gate trench 21; depositing so that an inside of the gate trench 21 may not be completely filled but some clearance may be left; embedding a nitride film 231 with respect to the clearance; performing an etch back of the nitride film 231 and the oxide film 23 by performing wet etching in such a state that the nitride film 231 is left inside the gate trench 21 because it is hardly etched; forming an oxide film 24 in a surface of a wall of the gate trench 21; depositing a gate material 22; and forming a source electrode and a drain electrode by etching the deposited gate material 22.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种绝缘栅型半导体器件，其中抑制了受接缝影响的击穿电压的劣化，并提供其制造方法。解决方案：该方法包括以下步骤：通过干蚀刻形成栅极沟槽21; 相对于栅沟槽21嵌入氧化膜23; 沉积，使得栅极沟槽21的内部可能不被完全填充，但可能留下一些间隙; 相对于间隙嵌入氮化物膜231; 在氮化膜231由于几乎不被蚀刻而留在栅极沟槽21内的状态下进行湿式蚀刻来进行氮化膜231和氧化物膜23的蚀刻; 在栅极沟槽21的壁表面形成氧化物膜24; 沉积栅极材料22; 并通过蚀刻沉积的栅极材料22形成源电极和漏电极。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005045123A Trench gate type semiconductor device and its manufacturing device 审中-公开
标题翻译： TRENCH门式半导体器件及其制造设备
公开(公告)号：JP2005045123A
公开(公告)日：2005-02-17
申请号：JP2003279293
申请日：2003-07-24
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , OKURA YASUTSUGU , KUROYANAGI AKIRA
IPC分类号： H01L29/41 , H01L21/336 , H01L29/417 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a trench gate type MOS FET of low ON resistance.
SOLUTION: An n
- -type drift region 2 and a p-channel region 3 are laminated one by one on an n
+ -type substrate 1. An n
+ -type source region 4 and a p
+ -type body region 5 are formed to a stripe in an upper surface of the p-channel region 3. A trench 7 passes through the p(n)-type channel region 3 and attains to the n
- -type drift region 2, and a gate 9 constituted of polycrystalline silicon is buried via a gate insulating film 8. The n
+ -type source region 4 and the p
+ -type body region 5 extend from the p(n)-type channel region 3 to a source electrode 20 and cross the trench 7. The upper surface of the gate 9 is located above the upper surface of the p-channel region 3. A layer insulating film 10 is inside the trench 7, and its upper surface is located below an opening of the trench 7. The source electrode 20, the n
+ -type source region 4 and the p
+ -type body region 5 are electrically connected each in a side wall of the trench 7.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供低导通电阻的沟槽栅型MOS FET。解决方案：将n - / SP>型漂移区2和p沟道区3逐层层叠在n + 型衬底1上.n 在p沟道区域3的上表面中形成有条纹的 + 型源极区域4和ap + 型体区域5.沟槽7通过 p（n）型沟道区3并达到n - SP型漂移区2，并且由多晶硅构成的栅极9通过栅极绝缘膜8埋入。n + 型源极区域4和p + 型体区域5从p（n）型沟道区域3延伸到源电极20并与沟槽7交叉。栅极9的上表面位于p沟道区域3的上表面之上。层间绝缘膜10位于沟槽7内，其上表面位于沟槽7的开口下方。源电极20 ，n + 型源区域4和p + 型体区域5分别电连接在一侧沟槽的墙壁7.版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2006128507A Insulated-gate semiconductor device and manufacturing method thereof 有权
标题翻译：绝缘栅半导体器件及其制造方法
公开(公告)号：JP2006128507A
公开(公告)日：2006-05-18
申请号：JP2004316912
申请日：2004-10-29
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , MIYAGI KYOSUKE , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/0623 , H01L29/0653 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide an insulated-gate semiconductor device and a manufacturing method thereof wherein high withstand voltage and compactness are made compatible. SOLUTION: In the semiconductor device 100, a gate trench 21 and a p-floating region 51 are formed in a cell area, and a terminating trench 62 and a p-floating region 53 are formed in a terminating area. Further, the inside of the terminating trench 621 among three terminating trenches 62 (terminating trench 621, terminating trench 622, terminating trench 623) has the same structure as the gate trench 21, and the other terminating trenches have a structure filled with an insulator such as silicon oxide etc. Further, the p-floating region 51 is formed by injecting an impurity from the underside of the gate trench 21, and the p-floating region 53 is formed by injecting an impurity from the underside of the terminating trench 62. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种绝缘栅半导体器件及其制造方法，其中高耐受电压和紧凑性被兼容。解决方案：在半导体器件100中，在单元区域中形成栅极沟槽21和p浮动区域51，并且在终止区域中形成端接沟槽62和p浮动区域53。此外，三个端接沟槽62（端接沟槽621，终端沟槽622，终止沟槽623）中的端接沟槽621的内部具有与栅极沟槽21相同的结构，并且其它端接沟槽具有填充有绝缘体的结构作为氧化硅等。此外，通过从栅沟槽21的下侧注入杂质形成p浮置区51，并且通过从终止沟62的下侧注入杂质形成p浮置区53。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005223255A Insulated gate semiconductor apparatus and its manufacturing process 有权
标题翻译：绝缘栅半导体器件及其制造工艺
公开(公告)号：JP2005223255A
公开(公告)日：2005-08-18
申请号：JP2004032001
申请日：2004-02-09
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , MIYAGI KYOSUKE , OKURA YASUTSUGU , TOKURA NORIHITO , KUROYANAGI AKIRA
IPC分类号： H01L21/3065 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/42368 , H01L29/513 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate semiconductor apparatus capable of suppressing device characteristic deterioration due to seam and void arising in a sedimentary insulating layer, and to provide a method for manufacturing the insulated gate semiconductor.
SOLUTION: This semiconductor apparatus is manufactured in the following processes: a gate trench 21 is formed by dry etching; an insulating film 23 with a good coating performance is embedded into the gate trench 21; a part of the insulating film 23 is etched back by dry etching; wet etching is conducted to cope with film damage; a gate oxide film 24 is formed on the wall of the gate trench 21; a cover insulating film 241 with an inadequate coating performance is formed in the gate trench 21, to seal a cuneate channel 233; a gate material 22 is accumulated; finally, the accumulated material 22 is etched so that source and drain electrodes are formed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种能够抑制由沉积绝缘层中产生的接缝和空隙引起的器件特性劣化的绝缘栅半导体器件，并提供一种制造绝缘栅极半导体的方法。解决方案：该半导体装置通过以下工艺制造：通过干蚀刻形成栅沟槽21; 具有良好涂层性能的绝缘膜23被嵌入到栅极沟槽21中; 绝缘膜23的一部分通过干蚀刻被回蚀刻; 进行湿法蚀刻以应对膜损坏; 栅极氧化膜24形成在栅极沟槽21的壁上; 在栅沟槽21中形成具有不良涂层性能的覆盖绝缘膜241，以密封楔形沟槽233; 堆积栅极材料22; 最后，对积聚的材料22进行蚀刻，形成源极和漏极。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2004363498A Power semiconductor device and method for manufacturing same 有权
公开(公告)号：JP2004363498A
公开(公告)日：2004-12-24
申请号：JP2003162866
申请日：2003-06-06
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , OKURA YASUTSUGU , KUROYANAGI AKIRA
IPC分类号： H01L21/336 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/0623 , H01L29/0634 , H01L29/42368 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide an element structure which can realize a MOS FET having a low ON resistance and a high breakdown voltage.
SOLUTION: In the power semiconductor device comprising a gate electrode 11 buried in a groove via a gate insulating film, a p-type depletion region enlargement layer 4 is provided between two n-type drift layers 3 and 5, and the groove is formed to reach the n-type drift layer 3. An n-type converted region the conduction type of which is converted to an n-type is formed in a region in the vicinity of the groove of the p type depletion region enlargement layer, thus forming a carrier path.
COPYRIGHT: (C)2005,JPO&NCIPI

9. 发明专利

JP2004214542A Vertical power mosfet 有权
公开(公告)号：JP2004214542A
公开(公告)日：2004-07-29
申请号：JP2003002161
申请日：2003-01-08
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , KUROYANAGI AKIRA
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a vertical power MOSFET capable of obtaining its low on-resistance without increasing the thickness of its gate oxide film.
SOLUTION: The vertical power MOSFET has an epitaxial layer 4 so formed on the surface of a substrate 1 having a drain electrode 2 on the rear surface thereof as to form an oxide-film layer 3 on the substrate 1, a body layer 5 provided on the surface of the epitaxial layer 4, source regions 7 provided at a part of the body layer 5, a trench gate 9 provided in a position interposed between the source regions 7 and so joined to the oxide-film layer 3 as not to contact with the substrate 1, and trench drains 11 so provided as to oppose the trench gate 9, as to be repeatedly alternated with the trench gate 9, and as to contact with the substrate 1 by passing through the oxide-film layer 3.
COPYRIGHT: (C)2004,JPO&NCIPI

10. 发明专利

JP2006093193A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006093193A
公开(公告)日：2006-04-06
申请号：JP2004273095
申请日：2004-09-21
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , OKURA YASUTSUGU , KUROYANAGI AKIRA , TOKURA NORIHITO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/42368 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can be manufactured simply by making a rise in breakdown voltage and the lowering of on-state resistance compatible, and to provide a method of manufacturing it. SOLUTION: The semiconductor device 100 includes an N + -type source region 31, a contact P + -type region 32, an N + -type drain region 11, a P - -type body region 41 and an N - -type drift region 12. Moreover, a gate trench of a step shape of formed by digging the part of the upper surface side of the semiconductor device 100 is provided. More particularly, an upper stage trench 21 with the wide width of the face of an opening and a lower stage trench 25 with the narrow width of the face of an opening are united, and the gate trench is constituted. The trench 21 and the trench 25 are different in depth. A P floating region 52 is formed under the upper stage trench 21, and a P floating region 51 is formed under the lower stage trench 25. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以通过使击穿电压升高和导通状态电阻的降低相容的制造简单地制造的半导体器件，并提供其制造方法。解决方案：半导体器件100包括N + SP /型源极区域31，触点P + 型区域32，N SP>型漏极区域11，P - SP型 - 类型体区域41和N - SP类型漂移区域12.此外，步骤形状的栅极沟槽提供了通过挖掘半导体器件100的上表面侧的一部分而形成的。更具体地，结合具有开口面宽宽的上级沟槽21和开口面的窄宽度的下级沟槽25，构成栅沟。沟槽21和沟槽25的深度不同。 P浮动区域52形成在上级沟槽21的下方，在下层沟槽25的下方形成有P浮动区域51.（C）2006，JPO＆NCIPI

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