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1. 发明申请

US20100185897A1 FAULT TOLERANT MEMORY APPARATUS, METHODS, AND SYSTEMS 有权
标题翻译：容错记忆装置，方法和系统
公开(公告)号：US20100185897A1
公开(公告)日：2010-07-22
申请号：US11693572
申请日：2007-03-29
申请人： Dennis C. Abts , Michael Higgins , Van L. Snyder
发明人： Dennis C. Abts , Michael Higgins , Van L. Snyder
IPC分类号： G06F11/14 , G06F11/07
CPC分类号： G06F11/141 , G06F11/106 , G11C11/401 , G11C29/44 , G11C2029/0409
摘要： Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.
摘要翻译：各种实施例包括容错存储器设备，方法和系统，包括包括包括多个可寻址存储器位置的存储器设备的设备以及耦合到存储器设备的存储器管理器，该存储器管理器包括调度单元，其可操作以检测多个从存储器件读取的数据中的位错误，并重试读取操作，以便区分间歇性错误和持续性错误。

2. 发明授权

US08464007B2 Systems and methods for read/write phase request servicing 有权
标题翻译：用于读/写相位请求服务的系统和方法
公开(公告)号：US08464007B2
公开(公告)日：2013-06-11
申请号：US12484075
申请日：2009-06-12
申请人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A Schwoerer
发明人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A Schwoerer
IPC分类号： G06F12/00
CPC分类号： G06F11/106 , G06F11/141 , G11C11/401 , G11C2029/0409 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.
摘要翻译：各种实施例包括容错存储器装置，方法和系统，包括用于向具有多个可寻址存储器位置的存储器件提供读取和写入请求的存储器管理器。存储器管理器包括多个存储体。每个银行都包含一个用于存储读取和写入请求的银行队列。存储器管理器还包括连接到多个存储体的请求仲裁器。请求仲裁器移除来自银行队列的读取和写入请求以呈现给存储器设备。请求仲裁器包括操作的读取阶段和操作的写入阶段，其中请求仲裁器在操作的读取阶段期间优先选择用于服务的读取请求，并且在写入操作期间优先选择用于服务的写入请求。

3. 发明授权

US08245087B2 Multi-bit memory error management 有权
标题翻译：多位内存错误管理
公开(公告)号：US08245087B2
公开(公告)日：2012-08-14
申请号：US11693572
申请日：2007-03-29
申请人： Dennis C. Abts , Michael Higgins , Van L. Snyder
发明人： Dennis C. Abts , Michael Higgins , Van L. Snyder
IPC分类号： G06F11/00
CPC分类号： G06F11/141 , G06F11/106 , G11C11/401 , G11C29/44 , G11C2029/0409
摘要： Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.
摘要翻译：各种实施例包括容错存储器设备，方法和系统，包括包括包括多个可寻址存储器位置的存储器设备的设备以及耦合到存储器设备的存储器管理器，该存储器管理器包括调度单元，其可操作以检测多个从存储器件读取的数据中的位错误，并重试读取操作，以便区分间歇性错误和持续性错误。

4. 发明申请

US20090287889A1 READ/WRITE CLUSTERING SYSTEMS AND METHODS 有权
标题翻译：读/写集群系统和方法
公开(公告)号：US20090287889A1
公开(公告)日：2009-11-19
申请号：US12484075
申请日：2009-06-12
申请人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A. Schwoerer
发明人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A. Schwoerer
IPC分类号： G06F12/00
CPC分类号： G06F11/106 , G06F11/141 , G11C11/401 , G11C2029/0409 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.
摘要翻译：各种实施例包括容错存储器装置，方法和系统，包括用于向具有多个可寻址存储器位置的存储器件提供读取和写入请求的存储器管理器。存储器管理器包括多个存储体。每个银行都包含一个用于存储读取和写入请求的银行队列。存储器管理器还包括连接到多个存储体的请求仲裁器。请求仲裁器移除来自银行队列的读取和写入请求以呈现给存储器设备。请求仲裁器包括操作的读取阶段和操作的写入阶段，其中请求仲裁器在操作的读取阶段期间优先选择用于服务的读取请求，并且在写入操作期间优先选择用于服务的写入请求。

5. 发明申请

US20090177932A1 METHOD AND APPARATUS FOR TRACKING, REPORTING AND CORRECTING SINGLE-BIT MEMORY ERRORS 有权
标题翻译：跟踪，报告和更正单位存储器错误的方法和装置
公开(公告)号：US20090177932A1
公开(公告)日：2009-07-09
申请号：US12274044
申请日：2008-11-19
申请人： Dennis C. Abts , Gerald A. Schwoerer , Van L. Snyder
发明人： Dennis C. Abts , Gerald A. Schwoerer , Van L. Snyder
IPC分类号： H03M13/05 , G06F11/00
CPC分类号： G06F11/141 , G06F11/106 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.
摘要翻译：各种实施例包括包括包括多个可寻址存储器位置的存储器件和耦合到存储器件的存储器管理器的设备，该存储器管理器包括调度单元和包括多个计数器的直方图数据结构，该调度单元可操作以检测从存储器件读取的数据中的单位错误，并且增加多个计数器中特定的一个计数器中的值，所述多个计数器中的特定一个计数器对应于所访问数据中的特定比特，读取数据中的位错误。

6. 发明授权

US08065573B2 Method and apparatus for tracking, reporting and correcting single-bit memory errors 有权
标题翻译：跟踪，报告和纠正单位内存错误的方法和装置
公开(公告)号：US08065573B2
公开(公告)日：2011-11-22
申请号：US12274044
申请日：2008-11-19
申请人： Dennis C. Abts , Gerald A Schwoerer , Van L. Snyder
发明人： Dennis C. Abts , Gerald A Schwoerer , Van L. Snyder
IPC分类号： G11C29/00
CPC分类号： G06F11/141 , G06F11/106 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.
摘要翻译：各种实施例包括包括包括多个可寻址存储器位置的存储器件和耦合到存储器件的存储器管理器的设备，该存储器管理器包括调度单元和包括多个计数器的直方图数据结构，该调度单元可操作以检测从存储器件读取的数据中的单位错误，并且增加多个计数器中特定的一个计数器中的值，所述多个计数器中的特定一个计数器对应于所访问数据中的特定比特，读取数据中的位错误。

7. 发明授权

US10449373B2 Connector enclosure assemblies of medical devices including an angled lead passageway 有权
公开(公告)号：US10449373B2
公开(公告)日：2019-10-22
申请号：US13449446
申请日：2012-04-18
申请人： Steven T. Deininger , Michael J. Baade , Katherine J. Bach , Van L. Snyder
发明人： Steven T. Deininger , Michael J. Baade , Katherine J. Bach , Van L. Snyder
IPC分类号： A61N1/37 , A61N1/375 , A61B90/50 , A61N1/18
摘要： Connector enclosure assemblies for medical devices provide an angled lead passageway. The lead passageway which is defined by electrical connectors and intervening seals within the connector enclosure assembly establishes the angle relative to a base plane of the connector enclosure assembly. Various other aspects may be included in conjunction with the angled lead passageway, including an angled housing of the connector enclosure assembly, feedthrough pins that extend to the electrical connectors where the feedthrough pins may include angled sections, and a set screw passageway set at an angle relative to the lead passageway to provide fixation of a lead within the lead passageway.

8. 发明申请

US20120203314A1 CONNECTOR ENCLOSURE ASSEMBLIES OF MEDICAL DEVICES INCLUDING AN ANGLED LEAD PASSAGEWAY 审中-公开
公开(公告)号：US20120203314A1
公开(公告)日：2012-08-09
申请号：US13449446
申请日：2012-04-18
申请人： Steven T. Deininger , Michael J. Baade , Katherine J. Bach , Van L. Snyder
发明人： Steven T. Deininger , Michael J. Baade , Katherine J. Bach , Van L. Snyder
IPC分类号： A61N1/36
摘要： Connector enclosure assemblies for medical devices provide an angled lead passageway. The lead passageway which is defined by electrical connectors and intervening seals within the connector enclosure assembly establishes the angle relative to a base plane of the connector enclosure assembly. Various other aspects may be included in conjunction with the angled lead passageway, including an angled housing of the connector enclosure assembly, feedthrough pins that extend to the electrical connectors where the feedthrough pins may include angled sections, and a set screw passageway set at an angle relative to the lead passageway to provide fixation of a lead within the lead passageway.

9. 发明授权

US08024638B2 Apparatus and method for memory read-refresh, scrubbing and variable-rate refresh 有权
标题翻译：用于存储器读取刷新，擦除和可变速率刷新的装置和方法
公开(公告)号：US08024638B2
公开(公告)日：2011-09-20
申请号：US11558450
申请日：2006-11-10
申请人： David R. Resnick , Van L. Snyder , Michael F. Higgins
发明人： David R. Resnick , Van L. Snyder , Michael F. Higgins
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读取刷新（也称为“分布式刷新”）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取存储器的每一行，其中来自不同列的数据在随后的读取刷新循环中读取行，直到读取每个列地址的所有行，如果找到则擦除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

10. 发明授权

US08126674B2 Memory-daughter-card-testing method and apparatus 有权
标题翻译：内存 - 子卡测试方法和设备
公开(公告)号：US08126674B2
公开(公告)日：2012-02-28
申请号：US12870516
申请日：2010-08-27
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G01R31/14 , G01R31/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

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