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1. 发明授权

US08464007B2 Systems and methods for read/write phase request servicing 有权
标题翻译：用于读/写相位请求服务的系统和方法
公开(公告)号：US08464007B2
公开(公告)日：2013-06-11
申请号：US12484075
申请日：2009-06-12
申请人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A Schwoerer
发明人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A Schwoerer
IPC分类号： G06F12/00
CPC分类号： G06F11/106 , G06F11/141 , G11C11/401 , G11C2029/0409 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.
摘要翻译：各种实施例包括容错存储器装置，方法和系统，包括用于向具有多个可寻址存储器位置的存储器件提供读取和写入请求的存储器管理器。存储器管理器包括多个存储体。每个银行都包含一个用于存储读取和写入请求的银行队列。存储器管理器还包括连接到多个存储体的请求仲裁器。请求仲裁器移除来自银行队列的读取和写入请求以呈现给存储器设备。请求仲裁器包括操作的读取阶段和操作的写入阶段，其中请求仲裁器在操作的读取阶段期间优先选择用于服务的读取请求，并且在写入操作期间优先选择用于服务的写入请求。

2. 发明授权

US08065573B2 Method and apparatus for tracking, reporting and correcting single-bit memory errors 有权
标题翻译：跟踪，报告和纠正单位内存错误的方法和装置
公开(公告)号：US08065573B2
公开(公告)日：2011-11-22
申请号：US12274044
申请日：2008-11-19
申请人： Dennis C. Abts , Gerald A Schwoerer , Van L. Snyder
发明人： Dennis C. Abts , Gerald A Schwoerer , Van L. Snyder
IPC分类号： G11C29/00
CPC分类号： G06F11/141 , G06F11/106 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.
摘要翻译：各种实施例包括包括包括多个可寻址存储器位置的存储器件和耦合到存储器件的存储器管理器的设备，该存储器管理器包括调度单元和包括多个计数器的直方图数据结构，该调度单元可操作以检测从存储器件读取的数据中的单位错误，并且增加多个计数器中特定的一个计数器中的值，所述多个计数器中的特定一个计数器对应于所访问数据中的特定比特，读取数据中的位错误。

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