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1. 发明申请

US20090287889A1 READ/WRITE CLUSTERING SYSTEMS AND METHODS 有权
标题翻译：读/写集群系统和方法
公开(公告)号：US20090287889A1
公开(公告)日：2009-11-19
申请号：US12484075
申请日：2009-06-12
申请人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A. Schwoerer
发明人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A. Schwoerer
IPC分类号： G06F12/00
CPC分类号： G06F11/106 , G06F11/141 , G11C11/401 , G11C2029/0409 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.
摘要翻译：各种实施例包括容错存储器装置，方法和系统，包括用于向具有多个可寻址存储器位置的存储器件提供读取和写入请求的存储器管理器。存储器管理器包括多个存储体。每个银行都包含一个用于存储读取和写入请求的银行队列。存储器管理器还包括连接到多个存储体的请求仲裁器。请求仲裁器移除来自银行队列的读取和写入请求以呈现给存储器设备。请求仲裁器包括操作的读取阶段和操作的写入阶段，其中请求仲裁器在操作的读取阶段期间优先选择用于服务的读取请求，并且在写入操作期间优先选择用于服务的写入请求。

2. 发明授权

US08464007B2 Systems and methods for read/write phase request servicing 有权
标题翻译：用于读/写相位请求服务的系统和方法
公开(公告)号：US08464007B2
公开(公告)日：2013-06-11
申请号：US12484075
申请日：2009-06-12
申请人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A Schwoerer
发明人： Dennis C. Abts , Michael Higgins , Van L. Snyder , Gerald A Schwoerer
IPC分类号： G06F12/00
CPC分类号： G06F11/106 , G06F11/141 , G11C11/401 , G11C2029/0409 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.
摘要翻译：各种实施例包括容错存储器装置，方法和系统，包括用于向具有多个可寻址存储器位置的存储器件提供读取和写入请求的存储器管理器。存储器管理器包括多个存储体。每个银行都包含一个用于存储读取和写入请求的银行队列。存储器管理器还包括连接到多个存储体的请求仲裁器。请求仲裁器移除来自银行队列的读取和写入请求以呈现给存储器设备。请求仲裁器包括操作的读取阶段和操作的写入阶段，其中请求仲裁器在操作的读取阶段期间优先选择用于服务的读取请求，并且在写入操作期间优先选择用于服务的写入请求。

3. 发明申请

US20090177932A1 METHOD AND APPARATUS FOR TRACKING, REPORTING AND CORRECTING SINGLE-BIT MEMORY ERRORS 有权
标题翻译：跟踪，报告和更正单位存储器错误的方法和装置
公开(公告)号：US20090177932A1
公开(公告)日：2009-07-09
申请号：US12274044
申请日：2008-11-19
申请人： Dennis C. Abts , Gerald A. Schwoerer , Van L. Snyder
发明人： Dennis C. Abts , Gerald A. Schwoerer , Van L. Snyder
IPC分类号： H03M13/05 , G06F11/00
CPC分类号： G06F11/141 , G06F11/106 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.
摘要翻译：各种实施例包括包括包括多个可寻址存储器位置的存储器件和耦合到存储器件的存储器管理器的设备，该存储器管理器包括调度单元和包括多个计数器的直方图数据结构，该调度单元可操作以检测从存储器件读取的数据中的单位错误，并且增加多个计数器中特定的一个计数器中的值，所述多个计数器中的特定一个计数器对应于所访问数据中的特定比特，读取数据中的位错误。

4. 发明授权

US08065573B2 Method and apparatus for tracking, reporting and correcting single-bit memory errors 有权
标题翻译：跟踪，报告和纠正单位内存错误的方法和装置
公开(公告)号：US08065573B2
公开(公告)日：2011-11-22
申请号：US12274044
申请日：2008-11-19
申请人： Dennis C. Abts , Gerald A Schwoerer , Van L. Snyder
发明人： Dennis C. Abts , Gerald A Schwoerer , Van L. Snyder
IPC分类号： G11C29/00
CPC分类号： G06F11/141 , G06F11/106 , G11C2029/0411 , H03M13/09
摘要： Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.
摘要翻译：各种实施例包括包括包括多个可寻址存储器位置的存储器件和耦合到存储器件的存储器管理器的设备，该存储器管理器包括调度单元和包括多个计数器的直方图数据结构，该调度单元可操作以检测从存储器件读取的数据中的单位错误，并且增加多个计数器中特定的一个计数器中的值，所述多个计数器中的特定一个计数器对应于所访问数据中的特定比特，读取数据中的位错误。

5. 发明申请

US20100318741A1 MULTIPROCESSOR COMPUTER CACHE COHERENCE PROTOCOL 审中-公开
标题翻译：多媒体计算机缓存协议协议
公开(公告)号：US20100318741A1
公开(公告)日：2010-12-16
申请号：US12483915
申请日：2009-06-12
申请人： Steven L. Scott , Gregory J. Faanes , Abdulla Bataineh , Michael Bye , Gerald A. Schwoerer , Dennis C. Abts
发明人： Steven L. Scott , Gregory J. Faanes , Abdulla Bataineh , Michael Bye , Gerald A. Schwoerer , Dennis C. Abts
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/084
摘要： A multiprocessor computer system comprises a processing node having a plurality of processors and a local memory shared among processors in the node. An L1 data cache is local to each of the plurality of processors, and an L2 cache is local to each of the plurality of processors. An L3 cache is local the node but shared among the plurality of processors, and the L3 cache is a subset of data stored in the local memory. The L2 caches are subsets of the L3 cache, and the L1 caches are a subset of the L2 caches in the respective processors.
摘要翻译：多处理器计算机系统包括具有多个处理器的处理节点和在节点中的处理器之间共享的本地存储器。 L1数据高速缓冲存储器是多个处理器中的每一个的本地，并且L2高速缓存对于多个处理器中的每个处理器是本地的。 L3高速缓存是本地节点，但是在多个处理器之间共享，并且L3高速缓存是存储在本地存储器中的数据的子集。 L2高速缓存是L3高速缓存的子集，L1高速缓存是相应处理器中的L2高速缓存的子集。

6. 发明申请

US20100185897A1 FAULT TOLERANT MEMORY APPARATUS, METHODS, AND SYSTEMS 有权
标题翻译：容错记忆装置，方法和系统
公开(公告)号：US20100185897A1
公开(公告)日：2010-07-22
申请号：US11693572
申请日：2007-03-29
申请人： Dennis C. Abts , Michael Higgins , Van L. Snyder
发明人： Dennis C. Abts , Michael Higgins , Van L. Snyder
IPC分类号： G06F11/14 , G06F11/07
CPC分类号： G06F11/141 , G06F11/106 , G11C11/401 , G11C29/44 , G11C2029/0409
摘要： Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.
摘要翻译：各种实施例包括容错存储器设备，方法和系统，包括包括包括多个可寻址存储器位置的存储器设备的设备以及耦合到存储器设备的存储器管理器，该存储器管理器包括调度单元，其可操作以检测多个从存储器件读取的数据中的位错误，并重试读取操作，以便区分间歇性错误和持续性错误。

7. 发明授权

US08245087B2 Multi-bit memory error management 有权
标题翻译：多位内存错误管理
公开(公告)号：US08245087B2
公开(公告)日：2012-08-14
申请号：US11693572
申请日：2007-03-29
申请人： Dennis C. Abts , Michael Higgins , Van L. Snyder
发明人： Dennis C. Abts , Michael Higgins , Van L. Snyder
IPC分类号： G06F11/00
CPC分类号： G06F11/141 , G06F11/106 , G11C11/401 , G11C29/44 , G11C2029/0409
摘要： Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.
摘要翻译：各种实施例包括容错存储器设备，方法和系统，包括包括包括多个可寻址存储器位置的存储器设备的设备以及耦合到存储器设备的存储器管理器，该存储器管理器包括调度单元，其可操作以检测多个从存储器件读取的数据中的位错误，并重试读取操作，以便区分间歇性错误和持续性错误。

8. 发明申请

US20150186318A1 DRAGONFLY PROCESSOR INTERCONNECT NETWORK 审中-公开
公开(公告)号：US20150186318A1
公开(公告)日：2015-07-02
申请号：US14583588
申请日：2014-12-27
申请人： John Kim , Dennis C. Abts , Steven L. Scott , William J. Dally
发明人： John Kim , Dennis C. Abts , Steven L. Scott , William J. Dally
IPC分类号： G06F13/40 , G06F9/455 , G06F13/42
CPC分类号： H04L49/15 , G06F9/45533 , G06F13/4027 , G06F13/4221 , G06F15/17375 , H04L45/28 , H04L45/58 , H04L49/1515 , H04L49/70
摘要： A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.
摘要翻译：多处理器计算机系统包括蜻蜓处理器互连网络，其包括多个处理器节点，多个路由器，每个路由器直接耦合到多个终端节点，彼此耦合并布置成一组的路由器，以及多个路由器组，使得每个组通过至少一个直接连接连接到彼此组。

9. 发明授权

US08306042B1 Class-based deterministic packet routing 失效
标题翻译：基于类的确定性分组路由
公开(公告)号：US08306042B1
公开(公告)日：2012-11-06
申请号：US12487832
申请日：2009-06-19
申请人： Dennis C. Abts
发明人： Dennis C. Abts
IPC分类号： H04L12/28 , G06F13/00
CPC分类号： H04L45/58 , G06F15/17312
摘要： Aspects of the invention pertain to deterministic packet routing systems and methods in multiprocessor computing architectures. Packets are analyzed to determine whether they are memory request packets or memory reply packets. Depending upon the packet, it is routed through nodes in the multiprocessor computer architecture in either an XY or YX path. Request and reply packets are sent in opposing routes according to a deterministic routing scheme. Multiport routers are placed at nodes in the architecture to pass the packets, using independent request and response virtual channels to avoid deadlock conditions.
摘要翻译：本发明的方面涉及多处理器计算架构中的确定性分组路由系统和方法。分析分组以确定它们是存储器请求分组还是存储器应答分组。根据数据包，它通过XY或YX路径中的多处理器计算机体系结构中的节点路由。根据确定性路由方案，以相反的路由发送请求和应答分组。多端口路由器放置在体系结构中的节点上，以通过独立的请求和响应虚拟通道传递数据包，以避免死锁状况。

10. 发明申请

US20120265883A1 MULTIPLE OVERLAPPING BLOCK TRANSFERS 审中-公开
标题翻译：多重重叠块传输
公开(公告)号：US20120265883A1
公开(公告)日：2012-10-18
申请号：US13448126
申请日：2012-04-16
申请人： Dennis C. Abts
发明人： Dennis C. Abts
IPC分类号： G06F15/173
CPC分类号： G06F13/124
摘要： A computerized system comprising multiple processing nodes, a physical channel configured to transfer data between a memory local to a processing node and a network target remote from the processing node, and a block transfer engine configured to allocate multiple virtual channels to the physical channel and to transfer multiple address-overlapping blocks of data simultaneously using the virtual channels.
摘要翻译：一种计算机化系统，包括多个处理节点，物理信道，被配置为在本地到处理节点的存储器与远离处理节点的网络目标之间传送数据;以及块传输引擎，被配置为向物理信道分配多个虚拟信道，使用虚拟通道同时传输多个地址重叠的数据块。

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