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1. 发明授权

US08024638B2 Apparatus and method for memory read-refresh, scrubbing and variable-rate refresh 有权
标题翻译：用于存储器读取刷新，擦除和可变速率刷新的装置和方法
公开(公告)号：US08024638B2
公开(公告)日：2011-09-20
申请号：US11558450
申请日：2006-11-10
申请人： David R. Resnick , Van L. Snyder , Michael F. Higgins
发明人： David R. Resnick , Van L. Snyder , Michael F. Higgins
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读取刷新（也称为“分布式刷新”）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取存储器的每一行，其中来自不同列的数据在随后的读取刷新循环中读取行，直到读取每个列地址的所有行，如果找到则擦除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

2. 发明授权

US07676728B2 Apparatus and method for memory asynchronous atomic read-correct-write operation 有权
标题翻译：用于存储器异步原子读取 - 正确写入操作的装置和方法
公开(公告)号：US07676728B2
公开(公告)日：2010-03-09
申请号：US11558452
申请日：2006-11-10
申请人： David R. Resnick , Van L. Snyder , Michael F. Higgins , Alan M. Grossmeier , Kelly J. Marquardt , Gerald A. Schwoerer
发明人： David R. Resnick , Van L. Snyder , Michael F. Higgins , Alan M. Grossmeier , Kelly J. Marquardt , Gerald A. Schwoerer
IPC分类号： G11C29/00
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读取刷新（也称为“分布式刷新”）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取存储器的每一行，其中来自不同列的数据在随后的读取刷新循环中读取行，直到读取每个列地址的所有行，如果找到则擦除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

3. 发明授权

US07320100B2 Apparatus and method for memory with bit swapping on the fly and testing 有权
标题翻译：用于存储器的装置和方法，用于在位上进行位交换和测试
公开(公告)号：US07320100B2
公开(公告)日：2008-01-15
申请号：US10850057
申请日：2004-05-19
申请人： R. Paul Dixon , David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard , Michael F. Higgins
发明人： R. Paul Dixon , David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard , Michael F. Higgins
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读取刷新（也称为“分布式刷新”）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取存储器的每一行，其中来自不同列的数据在随后的读取刷新循环中读取行，直到读取每个列地址的所有行，如果找到则擦除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

4. 发明申请

US20120246544A1 METHOD AND APPARATUS FOR MEMORY READ-REFRESH, SCRUBBING AND VARIABLE-RATE REFRESH 有权
标题翻译：存储器读取，刷新和可变速率刷新的方法和装置
公开(公告)号：US20120246544A1
公开(公告)日：2012-09-27
申请号：US13237676
申请日：2011-09-20
申请人： David R. Resnick , Van L. Snyder , Michael F. Higgins
发明人： David R. Resnick , Van L. Snyder , Michael F. Higgins
IPC分类号： H03M13/05 , G06F11/10 , G06F12/00
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读取刷新（也称为“分布式刷新”）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取存储器的每一行，其中来自不同列的数据在随后的读取刷新循环中读取行，直到读取每个列地址的所有行，如果找到则擦除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

5. 发明授权

US08347176B2 Method and apparatus for memory read-refresh, scrubbing and variable-rate refresh 有权
标题翻译：用于存储器读取刷新，擦除和可变速率刷新的方法和装置
公开(公告)号：US08347176B2
公开(公告)日：2013-01-01
申请号：US13237676
申请日：2011-09-20
申请人： David R. Resnick , Van L. Snyder , Michael F. Higgins
发明人： David R. Resnick , Van L. Snyder , Michael F. Higgins
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读刷新（也称为分布式刷新）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取每一行存储器，其中来自行内不同列的数据为在随后的读取刷新循环中读取，直到读取每个列地址的所有行，如果找到，则清除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

6. 发明授权

US08126674B2 Memory-daughter-card-testing method and apparatus 有权
标题翻译：内存 - 子卡测试方法和设备
公开(公告)号：US08126674B2
公开(公告)日：2012-02-28
申请号：US12870516
申请日：2010-08-27
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G01R31/14 , G01R31/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

7. 发明申请

US20100324854A1 MEMORY-DAUGHTER-CARD-TESTING METHOD AND APPARATUS 有权
标题翻译：记忆卡测试方法和装置
公开(公告)号：US20100324854A1
公开(公告)日：2010-12-23
申请号：US12870516
申请日：2010-08-27
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G06F19/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

8. 发明授权

US07565593B2 Apparatus and method for memory bit-swapping-within-address-range circuit 失效
标题翻译：存储器位交换内部地址范围电路的装置和方法
公开(公告)号：US07565593B2
公开(公告)日：2009-07-21
申请号：US11558454
申请日：2006-11-10
申请人： R. Paul Dixon , David R. Resnick , Van L. Snyder
发明人： R. Paul Dixon , David R. Resnick , Van L. Snyder
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读取刷新（也称为“分布式刷新”）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取存储器的每一行，其中来自不同列的数据在随后的读取刷新循环中读取行，直到读取每个列地址的所有行，如果找到则擦除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

9. 发明授权

US07826996B2 Memory-daughter-card-testing apparatus and method 有权
标题翻译：记忆子卡测试仪和方法
公开(公告)号：US07826996B2
公开(公告)日：2010-11-02
申请号：US11679175
申请日：2007-02-26
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G01C31/00 , G06F11/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一个MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

10. 发明授权

US07184916B2 Apparatus and method for testing memory cards 有权
标题翻译：用于测试存储卡的装置和方法
公开(公告)号：US07184916B2
公开(公告)日：2007-02-27
申请号：US10850044
申请日：2004-05-19
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G06F19/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

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