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1. 发明授权

US5897375A Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture 失效
标题翻译：用于铜的化学机械抛光（CMP）浆料和集成电路制造中的使用方法
公开(公告)号：US5897375A
公开(公告)日：1999-04-27
申请号：US954190
申请日：1997-10-20
申请人： David Watts , Rajeev Bajaj , Sanjit Das , Janos Farkas , Chelsea Dang , Melissa Freeman , Jaime A. Saravia , Jason Gomez , Lance B. Cook
发明人： David Watts , Rajeev Bajaj , Sanjit Das , Janos Farkas , Chelsea Dang , Melissa Freeman , Jaime A. Saravia , Jason Gomez , Lance B. Cook
IPC分类号： B24B37/00 , C09G1/02 , C09K3/14 , H01L21/304 , B24B1/00
CPC分类号： C23F3/00 , C09G1/02 , C09K3/1463 , C09K3/1472
摘要： A method for chemical mechanical polishing (CMP) a copper layer (22) begins by forming the copper layer (22). The copper layer (22) is then exposed to a slurry (24). The slurry (24) contains an oxidizing agent such as H.sub.2 O.sub.2, a carboxylate salt such as ammonium citrate, an abrasive slurry such as alumna abrasive, an optional triazole or triazole derivative, and a remaining balance of a solvent such as deionized water. The use of the slurry (24) polishes the copper layer (22) with a high rate of removal whereby pitting and corrosion of the copper layer (22) is reduced and good copper interconnect planarity is achieved. This slurry (24) has good selectivity of copper to oxide, and results in copper devices which have good electrical performance. In addition, disposal of the slurry (24) is not environmentally difficult since the slurry (24) is environmentally sound when compared to other prior art slurries.
摘要翻译：通过形成铜层（22）开始化学机械抛光（CMP）铜层（22）的方法。然后将铜层（22）暴露于浆料（24）。浆料（24）含有氧化剂如H 2 O 2，羧酸盐如柠檬酸铵，研磨浆如校准研磨剂，任选的三唑或三唑衍生物，剩余的溶剂如去离子水。浆料（24）的使用以高的去除速度抛光铜层（22），从而降低了铜层（22）的点蚀和腐蚀，并实现了良好的铜互连平面性。这种浆料（24）具有铜对氧化物的良好选择性，并且导致具有良好电性能的铜器件。此外，浆料（24）的处理不是环境困难的，因为与其它现有技术的浆料相比，浆料（24）是无害环境的。

2. 发明授权

US6001730A Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers 失效
标题翻译：用于抛光使用钽基阻挡层的铜互连的化学机械抛光（CMP）浆料
公开(公告)号：US6001730A
公开(公告)日：1999-12-14
申请号：US954191
申请日：1997-10-20
申请人： Janos Farkas , Rajeev Bajaj , Melissa Freeman , David K. Watts , Sanjit Das
发明人： Janos Farkas , Rajeev Bajaj , Melissa Freeman , David K. Watts , Sanjit Das
IPC分类号： C09G1/02 , H01L21/321 , H01L21/768 , H01L1/00
CPC分类号： H01L21/76873 , C09G1/02 , H01L21/3212 , H01L21/7684 , H01L21/76843 , H01L21/76877
摘要： A method for forming a copper interconnect on an integrated circuit (IC) begins by forming a dielectric layer (20) having an opening. A tantalum-based barrier layer (21), such as TaN or TaSiN, is formed within the opening in the layer (20). A copper layer (22) is formed over the barrier layer (21). A first CMP process is used to polish the copper (22) to expose portions of the barrier (21). A second CMP process which is different from the first CMP process is then used to polish exposed portions of the layer (21) faster than the dielectric layer (20) or the copper layer (22). After this two-step CMP process, a copper interconnect having a tantalum-based barrier is formed across the integrated circuit substrate (12).
摘要翻译：在集成电路（IC）上形成铜互连的方法通过形成具有开口的电介质层（20）开始。在层（20）的开口内形成有TaN或TaSiN等钽系阻挡层（21）。在阻挡层（21）的上方形成铜层（22）。第一CMP工艺用于抛光铜（22）以暴露阻挡层（21）的部分。然后使用与第一CMP工艺不同的第二CMP工艺来比电介质层（20）或铜层（22）更快地抛光层（21）的暴露部分。在该两步CMP工艺之后，跨越集成电路基板（12）形成具有钽基阻挡层的铜互连。

3. 发明授权

US5882243A Method for polishing a semiconductor wafer using dynamic control 失效
标题翻译：使用动态控制来研磨半导体晶片的方法
公开(公告)号：US5882243A
公开(公告)日：1999-03-16
申请号：US839996
申请日：1997-04-24
申请人： Sanjit Das , Subramoney Iyer , Olubunmi Adetutu , Rajeev Bajaj
发明人： Sanjit Das , Subramoney Iyer , Olubunmi Adetutu , Rajeev Bajaj
IPC分类号： B24B37/005 , B24B49/04 , B24B51/00
CPC分类号： B24B37/005 , B24B49/04
摘要： A polishing system (10) is used to polish a semiconductor wafer (16) in accordance with the present invention. Polishing system (10) includes a wafer carrier (14) which includes a modulation unit (20). Modulation unit (20) includes a plurality of capacitors made up of a flexible lower plate (22) and a plurality of smaller upper plate segments (24). A controller (40) monitors the capacitance between each smaller upper plate segment (24) and lower plate (22), and compares the measured capacitance against a predefined set capacitance. To the extent the measured capacitance and predefined capacitance are different, controller (40) adjusts the voltage being applied to the respective upper plate segment (24) so that the measured capacitance and predefined capacitance are aligned. Thus, the present invention is able to achieve dynamic and localized control of the shape of the wafer as it is being polished.
摘要翻译：根据本发明，抛光系统（10）用于抛光半导体晶片（16）。抛光系统（10）包括包括调制单元（20）的晶片载体（14）。调制单元（20）包括由柔性下板（22）和多个较小的上板段（24）组成的多个电容器。控制器（40）监测每个较小的上板段（24）和下板（22）之间的电容，并将测量的电容与预定的设定电容进行比较。在测量电容和预定电容不同的程度上，控制器（40）调节施加到相应的上板段（24）的电压，使得所测量的电容和预定电容对齐。因此，本发明能够在抛光时实现晶片的形状的动态和局部控制。

4. 发明申请

US20050242414A1 LOW-K INTERLEVEL DIELECTRIC LAYER (ILD) AND METHOD 失效
标题翻译： LOW-K交替介质层（ILD）和方法
公开(公告)号：US20050242414A1
公开(公告)日：2005-11-03
申请号：US10709320
申请日：2004-04-28
申请人： Matthew Angyal , Edward Barth , Sanjit Das , Charles Davis , Habib Hichri , William Landers , Jia Lee
发明人： Matthew Angyal , Edward Barth , Sanjit Das , Charles Davis , Habib Hichri , William Landers , Jia Lee
IPC分类号： H01L23/58
CPC分类号： H01L23/53295 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02362 , H01L21/31633 , H01L21/76829 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%-10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.
摘要翻译：层间电介质层（ILD）包括低k电介质层; 以及在压电应力下沉积在电介质层顶上的低k电介质膜。电介质层包括低k材料，例如有机硅玻璃（OSG）或SiCOH材料。电介质膜的厚度为电介质层厚度的2％-10％，与电介质层具有相似的化学成分，但具有与电介质层不同的形态。通过改变用于沉积低k电介质层的工艺，在介电层沉积的结束处或在其附近的压应力下沉积电介质膜。

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