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1. 发明授权

US5882243A Method for polishing a semiconductor wafer using dynamic control 失效
标题翻译：使用动态控制来研磨半导体晶片的方法
公开(公告)号：US5882243A
公开(公告)日：1999-03-16
申请号：US839996
申请日：1997-04-24
申请人： Sanjit Das , Subramoney Iyer , Olubunmi Adetutu , Rajeev Bajaj
发明人： Sanjit Das , Subramoney Iyer , Olubunmi Adetutu , Rajeev Bajaj
IPC分类号： B24B37/005 , B24B49/04 , B24B51/00
CPC分类号： B24B37/005 , B24B49/04
摘要： A polishing system (10) is used to polish a semiconductor wafer (16) in accordance with the present invention. Polishing system (10) includes a wafer carrier (14) which includes a modulation unit (20). Modulation unit (20) includes a plurality of capacitors made up of a flexible lower plate (22) and a plurality of smaller upper plate segments (24). A controller (40) monitors the capacitance between each smaller upper plate segment (24) and lower plate (22), and compares the measured capacitance against a predefined set capacitance. To the extent the measured capacitance and predefined capacitance are different, controller (40) adjusts the voltage being applied to the respective upper plate segment (24) so that the measured capacitance and predefined capacitance are aligned. Thus, the present invention is able to achieve dynamic and localized control of the shape of the wafer as it is being polished.
摘要翻译：根据本发明，抛光系统（10）用于抛光半导体晶片（16）。抛光系统（10）包括包括调制单元（20）的晶片载体（14）。调制单元（20）包括由柔性下板（22）和多个较小的上板段（24）组成的多个电容器。控制器（40）监测每个较小的上板段（24）和下板（22）之间的电容，并将测量的电容与预定的设定电容进行比较。在测量电容和预定电容不同的程度上，控制器（40）调节施加到相应的上板段（24）的电压，使得所测量的电容和预定电容对齐。因此，本发明能够在抛光时实现晶片的形状的动态和局部控制。

2. 发明授权

US6045435A Low selectivity chemical mechanical polishing (CMP) process for use on integrated circuit metal interconnects 失效
标题翻译：用于集成电路金属互连的低选择性化学机械抛光（CMP）工艺
公开(公告)号：US6045435A
公开(公告)日：2000-04-04
申请号：US905757
申请日：1997-08-04
申请人： Rajeev Bajaj , Subramoney Iyer , Thom Kobayashi , Jaime Saravia , Mark Fernandes , David K. Watts
发明人： Rajeev Bajaj , Subramoney Iyer , Thom Kobayashi , Jaime Saravia , Mark Fernandes , David K. Watts
IPC分类号： B24B37/04 , B24D13/14 , H01L21/321 , H01L21/768 , B24B1/00
CPC分类号： B24B37/24 , B24B37/042 , B24B37/26 , H01L21/3212 , H01L21/7684
摘要： A method for polishing a metal layer (20) containing a combination of wide features (12), low density features (14), and high density features (18), is illustrated. A hydrophilic polish pad (24) having a shore D hardness of greater than 50 is used along with slurry (22) containing silica and an acidic based oxidizer such as oxadic acid in a chemical mechanical polishing (CMP) process. The result is less than 5:1 and preferably 1:1. This low selectivity results in the metal layer (20) being polished to a level below the surface of the surrounding oxide in a timed-controlled polish.
摘要翻译：示出了用于抛光包含宽特征（12），低密度特征（14）和高密度特征（18）的组合的金属层（20）的方法。在化学机械抛光（CMP）工艺中，与含有二氧化硅和酸性氧化剂如草酸的浆料（22）一起使用具有大于50的肖氏D硬度的亲水抛光垫（24）。结果小于5：1，优选为1：1。这种低选择性导致金属层（20）以定时控制的抛光剂抛光到周围氧化物表面以下的水平。

3. 发明授权

US5885856A Integrated circuit having a dummy structure and method of making 失效
标题翻译：具有虚拟结构的集成电路及其制造方法
公开(公告)号：US5885856A
公开(公告)日：1999-03-23
申请号：US704481
申请日：1996-08-21
申请人： Percy V. Gilbert , Subramoney Iyer , Bradley P. Smith , Matthew A. Thompson , Kevin Kemp , Rajive Dhar
发明人： Percy V. Gilbert , Subramoney Iyer , Bradley P. Smith , Matthew A. Thompson , Kevin Kemp , Rajive Dhar
IPC分类号： H01L21/76 , H01L21/304 , H01L21/3105 , H01L21/762 , H01L21/768 , H01L21/70
CPC分类号： H01L21/31053 , H01L21/76229 , H01L21/76819
摘要： A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).
摘要翻译：在集成电路（10）的布局图案中添加了虚拟结构（20）的图案，以平衡半导体衬底（11）的表面上的抛光速率。每个虚拟结构（20）的位置是预定的，使得其不与阱边界（17）或有源区（21,27）相交，并且不会落在导电材料（例如多晶硅层22） 28）或互连结构（23,29）。

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