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1. 发明授权

US07242239B2 Programming and determining state of electrical fuse using field effect transistor having multiple conduction states 失效
标题翻译：使用具有多个导通状态的场效应晶体管来编程和确定电熔丝的状态
公开(公告)号：US07242239B2
公开(公告)日：2007-07-10
申请号：US11160056
申请日：2005-06-07
申请人： David R. Hanson , Dureseti Chidambarrao , Gregory J. Fredeman , David M. Onsongo
发明人： David R. Hanson , Dureseti Chidambarrao , Gregory J. Fredeman , David M. Onsongo
IPC分类号： H01H85/00
CPC分类号： G11C17/18
摘要： A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor (“multi-state FET”) having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage. The gate is operable to control operation of the multi-state FET in multiple states including a) an essentially nonconductive state; b) a first or “low” conductive state when a gate-source voltage exceeds the first threshold voltage, in which the multi-state FET is biased to conduct a relatively low magnitude current for determining the state of the fuse; and c) a second conductive state when the gate-source voltage exceeds the second threshold voltage, in which the multi-state FET is biased to conduct a relatively high magnitude programming current.
摘要翻译：提供了一种电路，其可操作以将电可更改元件（例如，熔丝或反熔丝）编程到编程状态，并确定电可更改元件是否处于编程状态。这种电路包括多导通状态场效应晶体管（“多状态FET”），其具有耦合到可电可变元件的源极或漏极中的至少一个，以将电流施加到电可更改元件。多状态FET具有第一阈值电压和第二阈值电压，两者均同时有效，第二阈值电压高于第一阈值电压。栅极可操作以控制多状态FET的操作，包括a）基本上非导通状态; b）当栅极 - 源极电压超过第一阈值电压时，第一或“低”导通状态，其中多态FET被偏置以传导相对低的幅度电流以确定保险丝的状态; 以及c）当所述栅极 - 源极电压超过所述第二阈值电压时，所述第二导电状态是所述多态FET被偏置以导通相对高的编程电流。

2. 发明授权

US07123529B1 Sense amplifier including multiple conduction state field effect transistor 有权
标题翻译：感应放大器包括多导通状态场效应晶体管
公开(公告)号：US07123529B1
公开(公告)日：2006-10-17
申请号：US11160054
申请日：2005-06-07
申请人： David R. Hanson , David M. Onsongo , Dureseti Chidambarrao
发明人： David R. Hanson , David M. Onsongo , Dureseti Chidambarrao
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C11/4091 , G11C2207/065
摘要： An integrated circuit is provided which includes a sensing circuit. In the sensing circuit, a pair of conductors including a first conductor and a second conductor are adapted to conduct a first differential signal having a small voltage difference and a second differential signal having a rail-to-rail voltage difference. A sense amplifier is coupled to the pair of conductors, the sense amplifier being operable to amplify the first differential signal into the second differential signal. The sensing circuit further includes a multiple conduction state field effect transistor or “multi-state FET” which has a source, a drain, and a gate operable to control conduction between the source and the drain. The multi-state FET has a first threshold voltage and a second threshold voltage which is effective at the same time as the first threshold voltage such that the multi-state FET is operable by the gate voltage to switch between an essentially nonconductive state, a first conductive state when a gate-source voltage applied between a gate and a source of the FET is between the first threshold voltage and the second threshold voltage, and a second conductive state when the gate voltage exceeds the second threshold voltage. The multi-state FET is used to perform an operation included in amplifying the first signal into the second signal by the sense amplifier.
摘要翻译：提供了一种集成电路，其包括感测电路。在感测电路中，包括第一导体和第二导体的一对导体适于传导具有小电压差的第一差分信号和具有轨至轨电压差的第二差分信号。感测放大器耦合到该对导体，读出放大器可操作以将第一差分信号放大为第二差分信号。感测电路还包括具有源极，漏极和栅极的多导通状态场效应晶体管或“多状态FET”，其可操作以控制源极和漏极之间的导通。多状态FET具有与第一阈值电压同时有效的第一阈值电压和第二阈值电压，使得多状态FET可由栅极电压操作，以在基本上非导通状态之间切换，第一阈值电压当施加在FET的栅极和源极之间的栅极 - 源极电压处于第一阈值电压和第二阈值电压之间时，导通状态，以及当栅极电压超过第二阈值电压时的第二导通状态。多态FET用于通过读出放大器执行将第一信号放大为第二信号所包含的操作。

3. 发明授权

US08405165B2 Field effect transistor having multiple conduction states 失效
标题翻译：具有多个导通状态的场效应晶体管
公开(公告)号：US08405165B2
公开(公告)日：2013-03-26
申请号：US11160055
申请日：2005-06-07
申请人： Dureseti Chidambarrao , David M. Onsongo , David R. Hanson
发明人： Dureseti Chidambarrao , David M. Onsongo , David R. Hanson
IPC分类号： H01L31/00
CPC分类号： H01L21/2822 , H01L29/42368 , H01L29/512 , H01L29/518
摘要： An FET including a gate conductor overlying a channel has first and second threshold voltages, respectively of a first and a second magnitude. When the second magnitude exceeds the first magnitude, both threshold voltages become effective concurrently. The FET operates responsive to a gate-source voltage between the gate conductor and source in states that include a non-conductive state. When the magnitude of the gate-source voltage is lower than the first and second magnitudes, the source-drain current is negligible. The first conductive state when the magnitude of the gate-source voltage exceeds the first magnitude and is lower than the second magnitude, the source-drain current operates at ten or more times exceeding the negligible value. When the second conductive state exceeds the magnitude of the gate-source voltage and exceeds the first and second magnitude, the state the source-drain current has a second operating value ten or more times higher than the first.
摘要翻译：包括覆盖在通道上的栅极导体的FET具有分别具有第一和第二幅度的第一和第二阈值电压。当第二幅度超过第一幅度时，两个阈值电压同时变得有效。 FET在包括非导通状态的状态下响应于栅极导体和源极之间的栅极 - 源极电压而起作用。当栅极 - 源极电压的幅度低于第一和第二幅度时，源极 - 漏极电流可以忽略不计。当栅极 - 源极电压的大小超过第一幅度且低于第二幅度时的第一导通状态，源极 - 漏极电流在超过可忽略的值的十次或更多次的情况下工作。当第二导电状态超过栅极 - 源极电压的幅度并超过第一和第二幅度时，源极 - 漏极电流具有比第一工作值高十倍或更多倍的第二工作值的状态。

4. 发明授权

US07337420B2 Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models 有权
标题翻译：基于布局的调制方法和紧凑模型中氮化物衬垫应力效应的优化
公开(公告)号：US07337420B2
公开(公告)日：2008-02-26
申请号：US11193711
申请日：2005-07-29
申请人： Dureseti Chidambarrao , Donald L. Jordan , Judith H. McCullen , David M. Onsongo , Tina Wagner , Richard Q. Williams
发明人： Dureseti Chidambarrao , Donald L. Jordan , Judith H. McCullen , David M. Onsongo , Tina Wagner , Richard Q. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , H01L29/7843
摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).
摘要翻译：用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。

5. 发明申请

US20070296001A1 MULTIPLE CONDUCTION STATE DEVICES HAVING DIFFERENTLY STRESSED LINERS 失效
标题翻译：具有不同应力衬层的多个导电状态器件
公开(公告)号：US20070296001A1
公开(公告)日：2007-12-27
申请号：US11425511
申请日：2006-06-21
申请人： Dureseti Chidambarrao , David M. Onsongo
发明人： Dureseti Chidambarrao , David M. Onsongo
IPC分类号： H01L29/768
CPC分类号： H01L29/7833 , H01L21/823412 , H01L29/665 , H01L29/7843 , Y10S438/938
摘要： A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.
摘要翻译：提供了一种场效应晶体管（“FET”），其包括包括沟道区，第一源极 - 漏极区和第二源极 - 漏极区的有源半导体区。有源半导体区域的主表面被分成相互排斥的第一部分和第二部分。第一衬里将第一应力施加到主表面的第一部分，并且第二衬里将第二应力施加到主表面的第二部分。第一和第二应力分别选自高拉伸应力，高压缩应力和中性应力，第一应力与第二应力不同。衬垫可以帮助区分在一个操作条件下由FET的第一部分传导的第一工作电流和在不同工作条件下由FET的第二部分传导的第二工作电流。

6. 发明授权

US07560326B2 Silicon/silcion germaninum/silicon body device with embedded carbon dopant 失效
标题翻译：硅/硅锗/硅体器件与嵌入式碳掺杂剂
公开(公告)号：US07560326B2
公开(公告)日：2009-07-14
申请号：US11381810
申请日：2006-05-05
申请人： Anda C. Mocuta , Dureseti Chidambarrao , Ricardo A. Donaton , David M. Onsongo , Kern Rim
发明人： Anda C. Mocuta , Dureseti Chidambarrao , Ricardo A. Donaton , David M. Onsongo , Kern Rim
IPC分类号： H01L21/8234 , H01L31/0392
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/66636 , H01L29/78687
摘要： A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.
摘要翻译：一种制造半导体器件的半导体结构和方法，特别是NFET器件。这些装置包括在应力诱导层上提供的应力接收层，其中在其间的界面处的材料减少了结构中失配位错的发生和传播。应力接收层是硅（Si），应力诱导层是硅锗（SiGe），并且材料是在形成器件期间通过掺杂层提供的碳。也可以在整个SiGe层中掺杂碳。

7. 发明授权

US07768041B2 Multiple conduction state devices having differently stressed liners 失效
标题翻译：具有不同应力衬垫的多导通状态器件
公开(公告)号：US07768041B2
公开(公告)日：2010-08-03
申请号：US11425511
申请日：2006-06-21
申请人： Dureseti Chidambarrao , David M. Onsongo
发明人： Dureseti Chidambarrao , David M. Onsongo
IPC分类号： H01L31/00
CPC分类号： H01L29/7833 , H01L21/823412 , H01L29/665 , H01L29/7843 , Y10S438/938
摘要： A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.
摘要翻译：提供了一种场效应晶体管（“FET”），其包括包括沟道区，第一源极 - 漏极区和第二源极 - 漏极区的有源半导体区。有源半导体区域的主表面被分成相互排斥的第一部分和第二部分。第一衬里将第一应力施加到主表面的第一部分，并且第二衬里将第二应力施加到主表面的第二部分。第一和第二应力分别选自高拉伸应力，高压缩应力和中性应力，第一应力与第二应力不同。衬垫可以帮助区分在一个操作条件下由FET的第一部分传导的第一工作电流和在不同工作条件下由FET的第二部分传导的第二工作电流。

8. 发明申请

US20080179636A1 N-FETS WITH TENSILELY STRAINED SEMICONDUCTOR CHANNELS, AND METHOD FOR FABRICATING SAME USING BURIED PSEUDOMORPHIC LAYERS 审中-公开
标题翻译：具有拉伸半导体通道的N-FET以及使用BURIED PSEUDOMORPHIC层的相同方法
公开(公告)号：US20080179636A1
公开(公告)日：2008-07-31
申请号：US11307224
申请日：2007-01-27
申请人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
发明人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
IPC分类号： H01L29/04 , H01L21/335 , H01L21/8238
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7849
摘要： The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.
摘要翻译：本发明涉及各自包含应变半导体通道的高性能n沟道场效应晶体管（n-FET），以及通过使用包含假象形成的压缩应变的掩埋伪晶层来形成这种n-FET的方法。

9. 发明授权

US07737500B2 CMOS diodes with dual gate conductors, and methods for forming the same 失效
标题翻译：具有双栅导体的CMOS二极管及其形成方法
公开(公告)号：US07737500B2
公开(公告)日：2010-06-15
申请号：US11380278
申请日：2006-04-26
申请人： David M. Onsongo , Werner Rausch , Haining S. Yang
发明人： David M. Onsongo , Werner Rausch , Haining S. Yang
IPC分类号： H01L23/62
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.
摘要翻译：本发明提供了具有双栅极导体的改进的CMOS二极管结构。具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度导体。

10. 发明申请

US20100252881A1 CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 有权
标题翻译：具有双栅导体的CMOS二极管及其形成方法
公开(公告)号：US20100252881A1
公开(公告)日：2010-10-07
申请号：US12814930
申请日：2010-06-14
申请人： David M. Onsongo , Werner Rausch , Haining S. Yang
发明人： David M. Onsongo , Werner Rausch , Haining S. Yang
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.
摘要翻译：本发明提供了具有双栅极导体的改进的CMOS二极管结构。具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度导体。

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