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1. 发明申请

US20080179636A1 N-FETS WITH TENSILELY STRAINED SEMICONDUCTOR CHANNELS, AND METHOD FOR FABRICATING SAME USING BURIED PSEUDOMORPHIC LAYERS 审中-公开
标题翻译：具有拉伸半导体通道的N-FET以及使用BURIED PSEUDOMORPHIC层的相同方法
公开(公告)号：US20080179636A1
公开(公告)日：2008-07-31
申请号：US11307224
申请日：2007-01-27
申请人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
发明人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
IPC分类号： H01L29/04 , H01L21/335 , H01L21/8238
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7849
摘要： The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.
摘要翻译：本发明涉及各自包含应变半导体通道的高性能n沟道场效应晶体管（n-FET），以及通过使用包含假象形成的压缩应变的掩埋伪晶层来形成这种n-FET的方法。

2. 发明授权

US07268049B2 Structure and method for manufacturing MOSFET with super-steep retrograded island 失效
标题翻译：具有超陡退化岛的MOSFET的制造和制造方法
公开(公告)号：US07268049B2
公开(公告)日：2007-09-11
申请号：US10954838
申请日：2004-09-30
申请人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

3. 发明授权

US07723750B2 MOSFET with super-steep retrograded island 失效
标题翻译：具超级陡峭退火岛的MOSFET
公开(公告)号：US07723750B2
公开(公告)日：2010-05-25
申请号：US11774221
申请日：2007-07-06
申请人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
IPC分类号： H01L29/737
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si1-x-yGexZy，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或它们的组合。

4. 发明授权

US06881635B1 Strained silicon NMOS devices with embedded source/drain 失效
标题翻译：具有嵌入式源极/漏极的应变硅NMOS器件
公开(公告)号：US06881635B1
公开(公告)日：2005-04-19
申请号：US10708746
申请日：2004-03-23
申请人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Haining S. Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Haining S. Yang , Huilong Zhu
IPC分类号： C30B25/18 , C30B29/06 , H01L21/20 , H01L21/285 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/786 , C30B23/00 , H01L21/36
CPC分类号： H01L29/78696 , C30B25/18 , C30B29/06 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/28562 , H01L29/1054 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7834 , H01L29/78687
摘要： A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.
摘要翻译：由SiGe层支撑的应变硅层上的平面NFET通过在晶体管本体外部并且在应变硅层下方除去SiGe材料并且利用外延硅替代去除的材料来实现降低的外部电阻，从而为晶体管电极提供较低电阻并允许更好地控制砷的扩散。

5. 发明授权

US06635517B2 Use of disposable spacer to introduce gettering in SOI layer 有权
标题翻译：使用一次性间隔物在SOI层中引入吸气
公开(公告)号：US06635517B2
公开(公告)日：2003-10-21
申请号：US09924014
申请日：2001-08-07
申请人： Tze-Chiang Chen , Thomas T. Hwang , Mukesh V. Khare , Effendi Leobandung , Anda C. Mocuta , Paul A. Ronsheim , Ghavam G. Shahidi
发明人： Tze-Chiang Chen , Thomas T. Hwang , Mukesh V. Khare , Effendi Leobandung , Anda C. Mocuta , Paul A. Ronsheim , Ghavam G. Shahidi
IPC分类号： H01L21335
CPC分类号： H01L29/66772 , H01L21/26506 , H01L21/3226 , H01L29/78654
摘要： A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.
摘要翻译：提供了在SOI衬底内形成自对准吸气区域的方法。具体地，本发明的方法包括以下步骤：在图案化的栅极堆叠区域的每个垂直侧壁上形成一次性间隔物，所述图案化栅极堆叠区域形成在SOI衬底的顶部含Si层上; 将吸气物质注入到不被一次性间隔物和图案化的栅堆叠区域保护的顶部含Si层中; 以及去除一次性间隔物并退火植入的吸气物质，以便将所述物种转化成吸气区域。

6. 发明申请

US20050242340A1 Strained silicon NMOS devices with embedded source/drain 审中-公开
公开(公告)号：US20050242340A1
公开(公告)日：2005-11-03
申请号：US11062993
申请日：2005-02-22
申请人： Dureseti Chidambarrao , Effendi Leobandung , Anda Mocuta , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Effendi Leobandung , Anda Mocuta , Haining Yang , Huilong Zhu
IPC分类号： C30B25/18 , C30B29/06 , H01L21/20 , H01L21/285 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/786 , H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072
CPC分类号： H01L29/78696 , C30B25/18 , C30B29/06 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/28562 , H01L29/1054 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7834 , H01L29/78687
摘要： A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.

7. 发明授权

US08723262B2 SOI FinFET with recessed merged fins and liner for enhanced stress coupling 有权
标题翻译： SOI FinFET具有凹入的合并翅片和衬垫，用于增强应力耦合
公开(公告)号：US08723262B2
公开(公告)日：2014-05-13
申请号：US13606893
申请日：2012-09-07
申请人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7843 , H01L29/6656 , H01L29/66795
摘要： FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.
摘要翻译： FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。一种方法包括向SOI衬底提供翅片，在鳍片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并鳍片，在栅极周围沉积虚拟间隔物，并使合并的膜片膜凹陷。然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。垂直硅化物提高了耐扩散性。

8. 发明授权

US08586449B1 Raised isolation structure self-aligned to fin structures 有权
标题翻译：升高的隔离结构自对准鳍结构
公开(公告)号：US08586449B1
公开(公告)日：2013-11-19
申请号：US13603872
申请日：2012-09-05
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Effendi Leobandung
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Effendi Leobandung
IPC分类号： H01L21/76
CPC分类号： H01L21/845 , H01L21/76229
摘要： Raised isolation structures can be formed at the same level as semiconductor fins over an insulator layer. A template material layer can be conformally deposited to fill the gaps among the semiconductor fins within each cluster of semiconductor fins on an insulator layer, while the space between adjacent clusters is not filled. After an anisotropic etch, discrete template material portions can be formed within each cluster region, while the buried insulator is physically exposed between cluster regions. A raised isolation dielectric layer is deposited and planarized to form raised isolation structures employing the template material portions as stopping structures. After removal of the template material portions, a cluster of semiconductor fins are located within a trench that is self-aligned to outer edges of the cluster of semiconductor fins. The trench can be employed to confine raised source/drain regions to be formed on the cluster of semiconductor fins.
摘要翻译：升高的隔离结构可以在与绝缘体层上的半导体鳍片相同的水平上形成。可以共形沉积模板材料层以填充绝缘体层上的每个半导体翅片簇内的半导体鳍片之间的间隙，而相邻簇之间的空间未被填充。在各向异性蚀刻之后，可以在每个簇区域内形成离散的模板材料部分，而埋入的绝缘体在簇区域之间物理暴露。沉积并平坦化凸起的隔离介电层以形成采用模板材料部分作为停止结构的凸起隔离结构。在去除模板材料部分之后，一组半导体鳍片位于与半导体鳍片簇的外边缘自对准的沟槽内。沟槽可以用来限制要形成在半导体鳍片簇上的凸起的源极/漏极区域。

9. 发明授权

US08513085B2 Structure and method to improve threshold voltage of MOSFETs including a high k dielectric 有权
标题翻译：提高包括高k电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US08513085B2
公开(公告)日：2013-08-20
申请号：US13409693
申请日：2012-03-01
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了阈值电压控制的半导体结构，其中共形含氮化物的衬垫位于具有大于氧化硅的介电常数的图案化栅极电介质材料的至少暴露的侧壁上。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

10. 发明申请

US20130173214A1 METHOD AND STRUCTURE FOR INLINE ELECTRICAL FIN CRITICAL DIMENSION MEASUREMENT 审中-公开
标题翻译：在线电度关键尺寸测量的方法和结构
公开(公告)号：US20130173214A1
公开(公告)日：2013-07-04
申请号：US13343186
申请日：2012-01-04
申请人： Tenko Yamashita , Huiming Bu , Effendi Leobandung , Theodorus Eduardus Standaert
发明人： Tenko Yamashita , Huiming Bu , Effendi Leobandung , Theodorus Eduardus Standaert
IPC分类号： G01B7/02 , H01L23/58 , G06F19/00
CPC分类号： G01B7/023 , G01B2210/56 , H01L22/12 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method and test circuit for electrically measuring the critical dimension of a fin of a FinFET is disclosed. The method comprises measuring the resistance of a first gate test structure, measuring the resistance of a second gate test structure, computing a linear equation relating sheet resistance to gate width, computing a Y intercept value of the linear equation to derive an external resistance value, computing a sheet resistance value for the first gate test structure based on the external resistance value, measuring the resistance of a doped fin test structure, and computing a critical dimension of a fin based on the sheet resistance value.
摘要翻译：公开了一种用于电测量FinFET的鳍的临界尺寸的方法和测试电路。该方法包括测量第一栅极测试结构的电阻，测量第二栅极测试结构的电阻，计算相关薄层电阻与栅极宽度的线性方程，计算线性方程的Y截距值以导出外部电阻值，基于外部电阻值计算第一栅极测试结构的薄层电阻值，测量掺杂散热片测试结构的电阻，以及基于薄层电阻值计算散热片的临界尺寸。

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