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1. 发明申请

US20080179636A1 N-FETS WITH TENSILELY STRAINED SEMICONDUCTOR CHANNELS, AND METHOD FOR FABRICATING SAME USING BURIED PSEUDOMORPHIC LAYERS 审中-公开
标题翻译：具有拉伸半导体通道的N-FET以及使用BURIED PSEUDOMORPHIC层的相同方法
公开(公告)号：US20080179636A1
公开(公告)日：2008-07-31
申请号：US11307224
申请日：2007-01-27
申请人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
发明人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
IPC分类号： H01L29/04 , H01L21/335 , H01L21/8238
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7849
摘要： The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.
摘要翻译：本发明涉及各自包含应变半导体通道的高性能n沟道场效应晶体管（n-FET），以及通过使用包含假象形成的压缩应变的掩埋伪晶层来形成这种n-FET的方法。

2. 发明授权

US07268049B2 Structure and method for manufacturing MOSFET with super-steep retrograded island 失效
标题翻译：具有超陡退化岛的MOSFET的制造和制造方法
公开(公告)号：US07268049B2
公开(公告)日：2007-09-11
申请号：US10954838
申请日：2004-09-30
申请人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

3. 发明授权

US07723750B2 MOSFET with super-steep retrograded island 失效
标题翻译：具超级陡峭退火岛的MOSFET
公开(公告)号：US07723750B2
公开(公告)日：2010-05-25
申请号：US11774221
申请日：2007-07-06
申请人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
IPC分类号： H01L29/737
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si1-x-yGexZy，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或它们的组合。

4. 发明授权

US06881635B1 Strained silicon NMOS devices with embedded source/drain 失效
标题翻译：具有嵌入式源极/漏极的应变硅NMOS器件
公开(公告)号：US06881635B1
公开(公告)日：2005-04-19
申请号：US10708746
申请日：2004-03-23
申请人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Haining S. Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Haining S. Yang , Huilong Zhu
IPC分类号： C30B25/18 , C30B29/06 , H01L21/20 , H01L21/285 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/786 , C30B23/00 , H01L21/36
CPC分类号： H01L29/78696 , C30B25/18 , C30B29/06 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/28562 , H01L29/1054 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7834 , H01L29/78687
摘要： A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.
摘要翻译：由SiGe层支撑的应变硅层上的平面NFET通过在晶体管本体外部并且在应变硅层下方除去SiGe材料并且利用外延硅替代去除的材料来实现降低的外部电阻，从而为晶体管电极提供较低电阻并允许更好地控制砷的扩散。

5. 发明申请

US20080179680A1 PSEUDOMORPHIC SI/SIGE/SI BODY DEVICE WITH EMBEDDED SIGE SOURCE/DRAIN 失效
标题翻译： PSEUDOMORPHIC SI / SIGE / SI身体装置与嵌入式信号源/排水
公开(公告)号：US20080179680A1
公开(公告)日：2008-07-31
申请号：US12054812
申请日：2008-03-25
申请人： Dureseti CHIDAMBARRAO , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
发明人： Dureseti CHIDAMBARRAO , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

6. 发明授权

US07691698B2 Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain 失效
标题翻译：具有嵌入式SiGe源极/漏极的假晶Si / SiGe / Si体器件
公开(公告)号：US07691698B2
公开(公告)日：2010-04-06
申请号：US11358483
申请日：2006-02-21
申请人： Dureseti Chidambarrao , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
发明人： Dureseti Chidambarrao , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

7. 发明授权

US08168971B2 Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain 失效
标题翻译：具有嵌入式SiGe源极/漏极的假晶Si / SiGe / Si体器件
公开(公告)号：US08168971B2
公开(公告)日：2012-05-01
申请号：US12054812
申请日：2008-03-25
申请人： Dureseti Chidambarrao , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
发明人： Dureseti Chidambarrao , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

8. 发明授权

US07560326B2 Silicon/silcion germaninum/silicon body device with embedded carbon dopant 失效
标题翻译：硅/硅锗/硅体器件与嵌入式碳掺杂剂
公开(公告)号：US07560326B2
公开(公告)日：2009-07-14
申请号：US11381810
申请日：2006-05-05
申请人： Anda C. Mocuta , Dureseti Chidambarrao , Ricardo A. Donaton , David M. Onsongo , Kern Rim
发明人： Anda C. Mocuta , Dureseti Chidambarrao , Ricardo A. Donaton , David M. Onsongo , Kern Rim
IPC分类号： H01L21/8234 , H01L31/0392
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/66636 , H01L29/78687
摘要： A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.
摘要翻译：一种制造半导体器件的半导体结构和方法，特别是NFET器件。这些装置包括在应力诱导层上提供的应力接收层，其中在其间的界面处的材料减少了结构中失配位错的发生和传播。应力接收层是硅（Si），应力诱导层是硅锗（SiGe），并且材料是在形成器件期间通过掺杂层提供的碳。也可以在整个SiGe层中掺杂碳。

9. 发明授权

US06635517B2 Use of disposable spacer to introduce gettering in SOI layer 有权
标题翻译：使用一次性间隔物在SOI层中引入吸气
公开(公告)号：US06635517B2
公开(公告)日：2003-10-21
申请号：US09924014
申请日：2001-08-07
申请人： Tze-Chiang Chen , Thomas T. Hwang , Mukesh V. Khare , Effendi Leobandung , Anda C. Mocuta , Paul A. Ronsheim , Ghavam G. Shahidi
发明人： Tze-Chiang Chen , Thomas T. Hwang , Mukesh V. Khare , Effendi Leobandung , Anda C. Mocuta , Paul A. Ronsheim , Ghavam G. Shahidi
IPC分类号： H01L21335
CPC分类号： H01L29/66772 , H01L21/26506 , H01L21/3226 , H01L29/78654
摘要： A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.
摘要翻译：提供了在SOI衬底内形成自对准吸气区域的方法。具体地，本发明的方法包括以下步骤：在图案化的栅极堆叠区域的每个垂直侧壁上形成一次性间隔物，所述图案化栅极堆叠区域形成在SOI衬底的顶部含Si层上; 将吸气物质注入到不被一次性间隔物和图案化的栅堆叠区域保护的顶部含Si层中; 以及去除一次性间隔物并退火植入的吸气物质，以便将所述物种转化成吸气区域。

10. 发明授权

US06916698B2 High performance CMOS device structure with mid-gap metal gate 失效
标题翻译：高性能CMOS器件结构，具有中间间隙金属栅极
公开(公告)号：US06916698B2
公开(公告)日：2005-07-12
申请号：US10795672
申请日：2004-03-08
申请人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
发明人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
IPC分类号： H01L29/423 , H01L21/8238 , H01L27/092 , H01L29/49
CPC分类号： H01L21/823807 , H01L21/823828
摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.
摘要翻译：公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如需要具有中间间隙金属栅极的CMOS器件。本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间））以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

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