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1. 发明申请

US20100252881A1 CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 有权
标题翻译：具有双栅导体的CMOS二极管及其形成方法
公开(公告)号：US20100252881A1
公开(公告)日：2010-10-07
申请号：US12814930
申请日：2010-06-14
申请人： David M. Onsongo , Werner Rausch , Haining S. Yang
发明人： David M. Onsongo , Werner Rausch , Haining S. Yang
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.
摘要翻译：本发明提供了具有双栅极导体的改进的CMOS二极管结构。具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度导体。

2. 发明授权

US07737500B2 CMOS diodes with dual gate conductors, and methods for forming the same 失效
标题翻译：具有双栅导体的CMOS二极管及其形成方法
公开(公告)号：US07737500B2
公开(公告)日：2010-06-15
申请号：US11380278
申请日：2006-04-26
申请人： David M. Onsongo , Werner Rausch , Haining S. Yang
发明人： David M. Onsongo , Werner Rausch , Haining S. Yang
IPC分类号： H01L23/62
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.
摘要翻译：本发明提供了具有双栅极导体的改进的CMOS二极管结构。具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度导体。

3. 发明授权

US08222702B2 CMOS diodes with dual gate conductors, and methods for forming the same 有权
标题翻译：具有双栅导体的CMOS二极管及其形成方法
公开(公告)号：US08222702B2
公开(公告)日：2012-07-17
申请号：US12814930
申请日：2010-06-14
申请人： David M. Onsongo , Werner Rausch , Haining S. Yang
发明人： David M. Onsongo , Werner Rausch , Haining S. Yang
IPC分类号： H01L21/70
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.
摘要翻译：本发明提供了具有双栅极导体的改进的CMOS二极管结构。具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度导体。

4. 发明申请

US20090008705A1 BODY-CONTACTED FINFET 有权
标题翻译：身体接触式FINFET
公开(公告)号：US20090008705A1
公开(公告)日：2009-01-08
申请号：US11773607
申请日：2007-07-05
申请人： Huilong Zhu , Thomas W. Dyer , Jack A. Mandelman , Werner Rausch
发明人： Huilong Zhu , Thomas W. Dyer , Jack A. Mandelman , Werner Rausch
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7842 , H01L29/66795 , H01L29/785
摘要： A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin.
摘要翻译：在半导体衬底上形成含硅翅片。在含硅翅片的底部周围形成氧化硅层。在含硅鳍上形成栅电介质，形成栅电极。在保护半导体翅片周围的通道的部分的同时，通过各向同性的蚀刻蚀刻含硅半导体鳍片的底部部分，从而在含硅鳍片上的finFET的通道和硅下方的下面的半导体层之间留下体带氧化层。翅片可以包括不均匀层的堆叠，其中底层被选择性地蚀刻到顶部半导体层。或者，翅片可以包括均匀的半导体材料，并且含硅翅片可以由含硅翅片的侧壁和顶表面上的电介质膜保护。

5. 发明授权

US07361959B2 CMOS circuits including a passive element having a low end resistance 有权
标题翻译： CMOS电路包括具有低端电阻的无源元件
公开(公告)号：US07361959B2
公开(公告)日：2008-04-22
申请号：US11164515
申请日：2005-11-28
申请人： Christopher D. Sheraw , Alyssa C. Bonnoit , K. Paul Muller , Werner Rausch
发明人： Christopher D. Sheraw , Alyssa C. Bonnoit , K. Paul Muller , Werner Rausch
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L21/26506 , H01L28/20 , H01L28/40 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，以及用于形成这种CMOS电路的方法。更具体地说，本发明涉及包含诸如埋地电阻器，电容器，二极管，电感器，衰减器，功率分配器和天线等无源元件的CMOS电路，其特征在于端接触电阻小于90欧姆微量元素这样的低端电阻可以通过将无源元件的间隔物宽度减小到约10nm至约30nm的范围，或通过在预非晶化注入步骤期间掩蔽无源元件来实现，使得无源元件基本上没有前非晶化植入物。

6. 发明申请

US20060076627A1 ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION 有权
标题翻译：通过外延界面有限扩散形成的超声结构
公开(公告)号：US20060076627A1
公开(公告)日：2006-04-13
申请号：US10711899
申请日：2004-10-12
申请人： Huajie Chen , Omer Dokumaci , Oleg Gluschenkov , Werner Rausch
发明人： Huajie Chen , Omer Dokumaci , Oleg Gluschenkov , Werner Rausch
IPC分类号： H01L29/94
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译：形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。更具体地，本发明增加了硅衬底的顶表面的氧含量。优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。这允许本发明在硅衬底的顶表面上外延生长硅层。此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

7. 发明申请

US20060065914A1 STRUCTURE AND METHOD FOR MAKING STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER 有权
公开(公告)号：US20060065914A1
公开(公告)日：2006-03-30
申请号：US10711637
申请日：2004-09-29
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

8. 发明申请

US20050054169A1 METHOD OF MANUFACTURE OF RAISED SOURCE DRAIN MOSFET WITH TOP NOTCHED GATE STRUCTURE FILLED WITH DIELECTRIC PLUG IN AND DEVICE MANUFACTURED THEREBY 审中-公开
标题翻译：具有插入电介质插入件的顶部注入栅结构的放大源漏MOSFET的制造方法及其制造方法
公开(公告)号：US20050054169A1
公开(公告)日：2005-03-10
申请号：US10605100
申请日：2003-09-09
申请人： Tina Wagner , Werner Rausch , Sadanand Deshpande
发明人： Tina Wagner , Werner Rausch , Sadanand Deshpande
IPC分类号： H01L21/336 , H01L29/786 , H01L21/331
CPC分类号： H01L29/66772 , H01L29/78618
摘要： A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A plug of dielectric material is formed in a notch in a cap layer above the gate polysilicon. The sidewalls of the gate electrode is covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.
摘要翻译：提供了一种用于形成具有形成在具有栅极电极堆叠的电介质层上的硅层的SOI MOSFET器件的方法，在栅电极堆叠的侧壁上具有侧壁间隔物，并且形成在硅层的表面上的升高的源极/漏极区域。栅极电极堆叠包括在形成于硅层的表面上的栅极电介质层上的多晶硅形成的栅电极。在栅多晶硅上方的帽层中的凹口中形成介电材料塞。为了消除栅极多晶硅的暴露，覆盖一部分插塞的侧壁间隔物覆盖栅电极的侧壁，从而避免在形成升高的源极/漏极区域期间形成假外延生长。

9. 发明授权

US5152849A Phosphating process 失效
标题翻译：磷化工艺
公开(公告)号：US5152849A
公开(公告)日：1992-10-06
申请号：US683106
申请日：1991-04-10
申请人： Klaus Bittner , Gerhard Muller , Werner Rausch , Klaus Wittel
发明人： Klaus Bittner , Gerhard Muller , Werner Rausch , Klaus Wittel
IPC分类号： C23C22/12 , C23C22/13 , C23C22/22 , C23C22/34 , C23C22/36
CPC分类号： C23C22/13 , C23C22/12 , C23C22/368
摘要： Disclosed is a process for phosphating a galvanized surface, particularly of galvanized steel wherein the surface is contacted for up to 10 seconds with a phosphating solution which contains accelerator, particularly nitrate,0.5 to 5.0 g/l zinc,3 to 20 g/l phosphate (calculated as P.sub.2 O.sub.5),0.3 to 3 g/l magnesiumat a weight ratio of magnesium: zinc=(0.5 to 10):1 and has an S value in the range from 0.2 to 0.4 preferably in the range from 0.2 to 0.3, and is replenished with a concentrate in which the weight ratio of zinc to phosphate (calculated as P.sub.2 O.sub.5) is in the range from (0 to 1):8.It is particularly desirable to use a phosphating solution which contains up to 1.5 g/l zinc, preferably 0.5 to 1 g/l zinc, at a weight ratio of magnesium: zinc of (0.5 to 3:1, nickel ions in an amount of up to 1.5 g/l, preferably in an amount of up to 0.5 g/l and simple or complex fluoride in an amount of up to 3 g/l, preferable 0.1 to 1.5 g/l (calculated as F in each case).A special advantage is afforded by the use of the process to treat galvanized steel strip which is subsequently painted or coated with a preformed organic film.
摘要翻译：公开了一种使镀锌表面，特别是镀锌钢板磷化的方法，其中表面与含有促进剂，特别是硝酸盐的磷酸盐溶液接触达10秒钟，0.5-5.0g / l锌，3-20g / l磷酸盐（以P 2 O 5计），0.3〜3g / l镁，镁：锌=（0.5〜10）：1的重量比，S值在0.2〜0.4的范围内，优选为0.2〜0.3，补充浓缩物，其中锌与磷酸盐的重量比（以P2O5计算）在（0至1）：8的范围内。特别希望使用含有1.5g / l以下锌，优选为0.5〜1g / l的锌，磷酸盐溶液，其重量比为：镁（0.5〜3:1），镍离子最多为1.5g / l，优选为至多0.5g / l的量，并且最多为3g / l的简单或复合氟化物，优选为0.1至1.5g / l（以每种情况计算为F）。通过使用该方法来处理随后涂覆或涂覆预成型有机膜的镀锌钢带提供了特别的优点。

10. 发明授权

US4559087A Process for phosphating metals 失效
标题翻译：磷化金属的工艺
公开(公告)号：US4559087A
公开(公告)日：1985-12-17
申请号：US600587
申请日：1984-04-17
申请人： Peter Jorns , Norbert Meyer , Werner Rausch , Josef Rothkegel , Gunther Luckhardt , Gudrun Volling
发明人： Peter Jorns , Norbert Meyer , Werner Rausch , Josef Rothkegel , Gunther Luckhardt , Gudrun Volling
IPC分类号： C23C22/73 , C23F7/10
CPC分类号： C23C22/73
摘要： In a process for phosphating composite metals containing steel and zinc surfaces using phosphating solutions based on zinc phosphate by the dipping process, in order to achieve satisfactory formation of the phosphate layer, the composite metals are subjected to preliminary dipping for a maximum of 30 seconds in a phosphating solution based on zinc phosphate in order to initiate the formation of the phosphate layer, and are then conveyed to the main dip-phosphating zone.It is advantageous to spray the composite metals with a phosphating solution based on zinc phosphate while they are being conveyed from the preliminary to the main dip-phosphating zone, and it is advisable to limit the duration of the conveying and thus of the spraying treatment to a maximum of 30 seconds.
摘要翻译：在使用通过浸渍法的磷酸锌的磷化液对含有钢和锌的表面进行磷酸化的复合金属的方法中，为了达到令人满意的磷酸盐层的形成，复合金属经过预浸渍最多30秒钟为了开始磷酸盐层的形成，以磷酸锌为基础的磷化液，然后被输送到主浸渍磷化区。在将磷酸盐从磷酸盐初步输送到主浸渍磷酸盐区时，用磷酸盐磷酸盐溶液喷雾复合金属是有利的，并且建议将输送的持续时间和喷雾处理限制在最多30秒。

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