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1. 发明申请

US20090072355A1 DUAL SHALLOW TRENCH ISOLATION STRUCTURE 审中-公开
标题翻译：双层隔离隔离结构
公开(公告)号：US20090072355A1
公开(公告)日：2009-03-19
申请号：US11856260
申请日：2007-09-17
申请人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Naoyoshi Kusaba
发明人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Naoyoshi Kusaba
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/76229 , H01L21/76232
摘要： A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths.
摘要翻译：在具有直的侧壁的第一浅沟槽上形成保护电介质层，同时暴露第二浅沟槽。在半导体衬底上形成氧化阻挡层。抗蚀剂被施加并凹入第二浅沟槽内。在凹陷的抗蚀剂上方去除氧化阻挡层。去除抗蚀剂并进行热氧化，使得在剩余的氧化掩模层上方形成热氧化物环。之后除去氧化阻挡层，并对其下方的暴露的半导体区域进行蚀刻以形成瓶状浅沟槽。第一和瓶形沟槽填充有电介质材料，分别形成直的侧壁浅沟槽隔离结构和瓶浅沟槽隔离结构。可以使用浅沟槽隔离结构来为具有不同深度的半导体器件提供最佳的电隔离和器件性能。

2. 发明申请

US20070267671A1 TRENCH CAPACITOR HAVING LATERAL EXTENSIONS IN ONLY ONE DIRECTION AND RELATED METHODS 审中-公开
标题翻译：具有仅一个方向的横向延伸的TRENCH电容器及相关方法
公开(公告)号：US20070267671A1
公开(公告)日：2007-11-22
申请号：US11383861
申请日：2006-05-17
申请人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Paul C. Parries , William C. Wille
发明人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Paul C. Parries , William C. Wille
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L29/66181
摘要： A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in only one direction, wherein the trench and each lateral extension are filled with a capacitor material. The lateral extensions increase surface area for the trench capacitor, but do not take up as much space as conventional structures.
摘要翻译：公开了一种沟槽电容器和相关方法，其包括具有从填充有电容器材料的沟槽的仅一个方向延伸的侧向延伸的沟槽。在一个实施例中，沟槽电容器包括在衬底内的沟槽，以及至少一个沿着一个方向从沟槽延伸的横向延伸部，其中沟槽和每个横向延伸部充满电容器材料。横向延伸增加了沟槽电容器的表面积，但不占用与常规结构相同的空间。

3. 发明申请

US20120305940A1 Defect Free Si:C Epitaxial Growth 审中-公开
标题翻译：缺陷Si：C外延生长
公开(公告)号：US20120305940A1
公开(公告)日：2012-12-06
申请号：US13151238
申请日：2011-06-01
申请人： Thomas N. Adam , Stephen W. Bedell , Bruce B. Doris , Lisa F. Edge , Keith E. Fogel , Johnathan E. Faltermeier , Jinghong Li , Alexander Reznicek , Devendra K. Sadana , Bin Yang
发明人： Thomas N. Adam , Stephen W. Bedell , Bruce B. Doris , Lisa F. Edge , Keith E. Fogel , Johnathan E. Faltermeier , Jinghong Li , Alexander Reznicek , Devendra K. Sadana , Bin Yang
IPC分类号： H01L29/24 , H01L21/20
CPC分类号： H01L21/02529 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L29/045 , H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.
摘要翻译：公开了在NFET器件中的无缺陷Si：C源极/漏极的方法和结构。接受具有{100}晶体取向的主表面的晶片。以这样的方式在晶片中形成凹部，使得凹部的底表面和四个侧壁表面都具有{100}晶体取向。 Si：C材料在凹槽中被轴向生长，并且由于晶体取向，邻近四个侧壁表面的缺陷密度基本上与下表面相同。外延填充的凹槽用于NFET器件的源极/漏极制造。 NFET器件沿着<100>结晶方向取向，由于源极/漏极中的缺陷Si：C，器件沟道处于拉伸应变状态。

4. 发明授权

US08309447B2 Method for integrating multiple threshold voltage devices for CMOS 有权
标题翻译：用于集成多个CMOS阈值电压器件的方法
公开(公告)号：US08309447B2
公开(公告)日：2012-11-13
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译：公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。因此，本公开的方法避免了短信道惩罚。此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

5. 发明申请

US20120040522A1 METHOD FOR INTEGRATING MULTIPLE THRESHOLD VOLTAGE DEVICES FOR CMOS 有权
标题翻译：用于集成用于CMOS的多个阈值电压器件的方法
公开(公告)号：US20120040522A1
公开(公告)日：2012-02-16
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译：公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。因此，本公开的方法避免了短信道惩罚。此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

6. 发明申请

US20110303981A1 Scheme to Enable Robust Integration of Band Edge Devices and Alternatives Channels 审中-公开
标题翻译：实现带边缘设备和替代通道鲁棒集成的方案
公开(公告)号：US20110303981A1
公开(公告)日：2011-12-15
申请号：US12797431
申请日：2010-06-09
申请人： Lisa F. Edge , Hemanth Jagannathan , Bala Subramanian Haran
发明人： Lisa F. Edge , Hemanth Jagannathan , Bala Subramanian Haran
IPC分类号： H01L27/12 , H01L21/20
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L21/845
摘要： A method of forming a semiconductor device includes forming a buried oxide (BOX) layer on a semiconductor substrate, forming a silicon-on-insulator (SOI) layer on the BOX layer, depositing a hard mask including one of silicon, a nitride, and a metal oxide on the SOI layer, removing the hard mask from a first region of the semiconductor device, performing a cleaning process on the semiconductor device, wherein the hard mask is not removed from a second region of the semiconductor device by the cleaning process, epitaxially growing a semiconductor material in the first region of the semiconductor device, and removing the hard mask from the second region of the semiconductor device.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成掩埋氧化物（BOX）层，在BOX层上形成绝缘体上硅（SOI）层，沉积包括硅，氮化物和所述SOI层上的金属氧化物，从所述半导体器件的第一区域去除所述硬掩模，对所述半导体器件执行清洁处理，其中所述硬掩模不通过所述清洁处理从所述半导体器件的第二区域移除，在半导体器件的第一区域中外延生长半导体材料，以及从半导体器件的第二区域去除硬掩模。

7. 发明申请

US20110081765A1 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 有权
标题翻译：提高生产费用总额的方法
公开(公告)号：US20110081765A1
公开(公告)日：2011-04-07
申请号：US12571483
申请日：2009-10-01
申请人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

8. 发明授权

US09059314B2 Structure and method to obtain EOT scaled dielectric stacks 有权
标题翻译：获得EOT缩放电介质叠层的结构和方法
公开(公告)号：US09059314B2
公开(公告)日：2015-06-16
申请号：US13602118
申请日：2012-09-01
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

9. 发明授权

US08304836B2 Structure and method to obtain EOT scaled dielectric stacks 有权
标题翻译：获得EOT缩放电介质堆叠的结构和方法
公开(公告)号：US08304836B2
公开(公告)日：2012-11-06
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

10. 发明申请

US20120126295A1 BORDERLESS CONTACT FOR REPLACEMENT GATE EMPLOYING SELECTIVE DEPOSITION 有权
标题翻译：无边界联系人选择选择性沉积
公开(公告)号：US20120126295A1
公开(公告)日：2012-05-24
申请号：US12952372
申请日：2010-11-23
申请人： Lisa F. Edge , Balasubramanian S. Haran
发明人： Lisa F. Edge , Balasubramanian S. Haran
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823871 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.
摘要翻译：可以使用自对准栅极帽电介质来形成与扩散区域的自对准接触，同时防止由于覆盖变化导致的栅极导体的电短路。在一个实施例中，可电镀或无电镀的金属被选择性地沉积在栅电极中的导电材料上，同时金属不沉积在电介质表面上。栅极顶部的金属部分被转换成包括金属和氧的栅极电介质。在另一个实施例中，在电介质表面上形成自组装单层，同时暴露栅电极的金属顶表面。在未被自组装单层覆盖的区域上形成包括电介质氧化物的栅极电介质。栅极电介质在形成通孔期间用作蚀刻停止结构，从而避免了在其中形成的接触通孔结构与栅电极之间的电短路。

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