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1. 发明申请

US20090029541A1 METHOD OF FABRICATING ANTI-FUSE AND METHOD OF PROGRAMMING ANTI-FUSE 审中-公开
标题翻译：制造抗融合物的方法和编程抗体的方法
公开(公告)号：US20090029541A1
公开(公告)日：2009-01-29
申请号：US12211608
申请日：2008-09-16
申请人： Kuang-Yeh Chang , Shing-Ren Sheu , Chung Jen Ho
发明人： Kuang-Yeh Chang , Shing-Ren Sheu , Chung Jen Ho
IPC分类号： H01L21/44
CPC分类号： H01L23/5252 , H01L21/26586 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an anti-fuse includes firstly forming a dielectric layer on a substrate having a first conductive type. Next, a conductive layer is formed on the dielectric layer. A first ion implantation process is then performed, such that the conductive layer has the first conductive type. Thereafter, the conductive layer and the dielectric layer are patterned to form a gate and a gate dielectric layer. The gate and the gate dielectric layer together construct a gate structure. Finally, two source/drain regions having a second conductive type are formed in the substrate at respective sides of the gate. Besides, a method of programming an anti-fuse includes firstly applying a voltage to a gate to break down a gate dielectric layer. The gate and a substrate are then electrically conducted or a P/N forward bias is then formed in a P/N junction after the breakdown of the gate dielectric layer.
摘要翻译：制造抗熔丝的方法包括首先在具有第一导电类型的衬底上形成电介质层。接下来，在电介质层上形成导电层。然后执行第一离子注入工艺，使得导电层具有第一导电类型。此后，对导电层和电介质层进行构图以形成栅极和栅极电介质层。栅极和栅极电介质层一起构成栅极结构。最后，具有第二导电类型的两个源极/漏极区域形成在栅极的相应侧的衬底中。此外，编制反熔丝的方法包括首先向栅极施加电压以分解栅极电介质层。然后对栅极和衬底进行电导或在栅极电介质层击穿之后在P / N结中形成P / N正向偏压。

2. 发明授权

US6130839A Methods of programming, erasing and reading a flash memory 有权
标题翻译：编程，擦除和读取闪存的方法
公开(公告)号：US6130839A
公开(公告)日：2000-10-10
申请号：US179738
申请日：1998-10-27
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , H01L21/336
CPC分类号： H01L29/66825 , G11C16/0416 , G11C16/10 , G11C16/16
摘要： A flash memory comprises a plurality of word lines, a plurality of source lines and a plurality of bit lines, the word lines are arranged in a matrix with the bit lines and the source lines, respectively. Between every two adjacent bit line and source line and on every word line there forms a memory cell. Each bit line and source line are coupled to memory cells of two columns. During the procedure of "erase", two columns of memory cells can be erased at the same time. Methods of programming, erasing and reading the flash memory are much easy and controllable.
摘要翻译：闪速存储器包括多个字线，多个源极线和多个位线，字线分别以位线和源极线排列成矩阵。在每两个相邻位线和源极线之间以及每个字线上形成一个存储单元。每个位线和源极线耦合到两列的存储单元。在“擦除”过程中，可以同时擦除两列存储单元。编程，擦除和读取闪存的方法很容易和可控。

3. 发明授权

US06107666A High density ROM and a method of making the same 失效
标题翻译：高密度ROM及其制作方法
公开(公告)号：US06107666A
公开(公告)日：2000-08-22
申请号：US53023
申请日：1998-04-01
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： G11C17/10 , H01L21/822 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/101 , G11C17/10 , H01L21/822
摘要： The method includes forming a first insulating layer over a substrate. A first metal layer is formed over the first insulating layer. The first metal layer is patterned to form a plurality of parallel bit lines. A second insulating layer is formed over the bit lines and first insulating layer. At least one via is formed in the second insulating layer. Tungsten fills the via to form a tungsten plug. A second metal layer is formed over the second insulating layer. The second metal layer is patterned to form a plurality of parallel word lines. The word lines and the bit lines crosses at an angle. The present invention is also directed toward a high density ROM device that comprises a substrate and at least one memory array, including a first insulating layer located over a surface of the substrate, and a bit line located on a surface of the first insulating layer. The memory array further includes a second insulating layer formed on a surface of the bit line, and at least one via is formed in the second insulating layer and is in communication with the bit line. Plural word lines are located on a surface of the second insulating layer. The bit lines and the word lines cross at an angle.
摘要翻译：该方法包括在衬底上形成第一绝缘层。在第一绝缘层上形成第一金属层。图案化第一金属层以形成多个并行位线。第二绝缘层形成在位线和第一绝缘层之上。在第二绝缘层中形成至少一个通孔。钨填充通孔以形成钨丝塞。在第二绝缘层上形成第二金属层。图案化第二金属层以形成多个平行字线。字线和位线以一定角度交叉。本发明还涉及一种高密度ROM器件，其包括衬底和至少一个存储器阵列，其包括位于衬底表面上的第一绝缘层和位于第一绝缘层的表面上的位线。存储器阵列还包括形成在位线的表面上的第二绝缘层，并且至少一个通孔形成在第二绝缘层中并与位线连通。多个字线位于第二绝缘层的表面上。位线和字线以一定角度交叉。

4. 发明授权

US5981357A Semiconductor trench isolation with improved planarization methodology 失效
标题翻译：具有改进的平面化方法的半导体沟槽隔离
公开(公告)号：US5981357A
公开(公告)日：1999-11-09
申请号：US877000
申请日：1997-06-16
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

5. 发明授权

US5962914A Reduced bird's beak field oxidation process using nitrogen implanted into active region 有权
公开(公告)号：US5962914A
公开(公告)日：1999-10-05
申请号：US168761
申请日：1998-10-08
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L24/36
CPC分类号： H01L21/76213
摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.

6. 发明授权

US5937310A Reduced bird's beak field oxidation process using nitrogen implanted into active region 失效
标题翻译：使用植入活动区域的氮减少鸟的喙场氧化过程
公开(公告)号：US5937310A
公开(公告)日：1999-08-10
申请号：US639758
申请日：1996-04-29
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/265 , H01L21/316 , H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/26506 , H01L21/31662 , H01L21/32 , H01L21/76213 , Y10S438/981
摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.
摘要翻译：在不使用氮化硅的情况下形成自对准场氧化物隔离结构的方法。该方法包括在半导体衬底的上表面上形成电介质。半导体衬底的上表面包括相互横向相邻的有源区和隔离区。在植入电介质的顶部上构图光致抗蚀剂层，以在有源区域上暴露植入电介质的区域。然后通过植入电介质将氮注入有源区。氮优选以0.5至2.0％的近似原子浓度引入半导体衬底。在将氮气注入到半导体衬底中之后，剥离光致抗蚀剂层并除去注入电介质。然后将晶片热氧化，使得具有第一厚度的场氧化物在隔离区上生长，并且在有源区上生长具有第二厚度的薄氧化物。半导体衬底内的氮的存在阻碍了有源区中硅的氧化速率，使得薄氧化物的厚度基本上小于热氧化物的厚度。在目前优选的实施例中，场氧化物的厚度为2,000至8,000埃，而薄氧化物的厚度小于300埃。

7. 发明授权

US5926417A Read method for reading data from a high-density semiconductor read-only memory device 失效
标题翻译：用于从高密度半导体只读存储器件读取数据的读取方法
公开(公告)号：US5926417A
公开(公告)日：1999-07-20
申请号：US965502
申请日：1997-11-06
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： G11C17/00 , G11C17/10 , G11C16/04
CPC分类号： G11C17/10 , G11C17/00
摘要： A read method for reading data from a ROM device is provided, which can be operated with a higher voltage to address the memory cells in the ROM device. The ROM device are formed with word and bit lines formed from metallization layers having a very low resistance so that the data current can be increased for increased performance. This read method is for use on a ROM device of the type including an array of memory cells formed at the intersections between a plurality of word lines and a plurality of bit lines. Of these memory cells, a first selected group are set to a permanently-ON state due to the forming of a contact window connecting the associated word line to the associated bit line, and a second selected group of the memory cells are set to a permanently-OFF state due to the forming of no contact window therein. The read method includes the steps of applying a high potential to the associated bit line of the currently addressed one of the memory cells while floating all of the other bit lines, and meanwhile applying a ground potential to the associated word line of the currently addressed one of the memory cells while floating all of the other word lines.
摘要翻译：提供了一种用于从ROM装置读取数据的读取方法，其可以以更高的电压操作以对ROM装置中的存储器单元寻址。 ROM器件形成有由具有非常低电阻的金属化层形成的字和位线，使得可以增加数据电流以增加性能。该读取方法用于包括形成在多个字线和多个位线之间的交叉处的存储单元阵列的类型的ROM器件。在这些存储单元中，由于形成将相关联的字线连接到相关联的位线的接触窗口，将第一选定组设置为永久接通状态，并且将第二选定组的存储器单元设置为永久地由于在其中形成没有接触窗口的-OFF状态。读取方法包括以下步骤：在浮动所有其它位线时将高电位施加到当前寻址的存储单元的相关位线，同时将地电位施加到当前寻址的一个的相关字线的存储单元，同时浮动所有其他字线。

8. 发明授权

US5877049A Method for forming advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits 失效
标题翻译：用于形成具有用于高密度/高性能集成电路的最佳短通道控制的先进晶体管结构的方法
公开(公告)号：US5877049A
公开(公告)日：1999-03-02
申请号：US717981
申请日：1996-09-23
申请人： Yowjuang W. Liu , Kuang-Yeh Chang
发明人： Yowjuang W. Liu , Kuang-Yeh Chang
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7832 , H01L21/823807 , H01L27/0928 , H01L29/1075 , H01L29/1087 , H01L29/6659 , Y10S257/901
摘要： A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.
摘要翻译：通过改善短沟道控制来提高器件缩放的新型MOS晶体管结构包括在MOS晶体管的沟道区下面的掩埋后栅极。与通过电气传递到掩埋后门的阱的单独接触改善了短通道控制而没有性能下降。在优选实施例中，当关闭n沟道MOS晶体管时，背栅极接地。在替代实施例中，掩埋层产生逆行p阱。在一些应用中，可以使用多个掩埋层，其中一个或多个是平面的。 CMOS器件可能具有独立的多重埋后栅。

9. 发明授权

US5874339A Method of making a ROM diode 失效
标题翻译：制造ROM二极管的方法
公开(公告)号：US5874339A
公开(公告)日：1999-02-23
申请号：US808257
申请日：1997-02-28
申请人： Kuang-Yeh Chang
发明人： Kuang-Yeh Chang
IPC分类号： H01L21/8229 , H01L27/102 , H01L21/8246
CPC分类号： H01L27/1021 , H01L21/8229
摘要： A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. An N well is formed in the P-type substrate, wherein some of the silicon nitride layer is over the N well. A field oxide layer is formed over the substrate. The silicon nitride layer is removed. The N well is doped using first P-type ions to form a plurality of essentially parallel P-pole regions. An insulating layer is formed over the field oxide layer. A plurality of contact windows are formed within the insulating layer to expose a portion of the P-pole regions. The N well is doped and annealed, to form a plurality of P-type diffusion regions under the exposed portions of the P-pole regions. The P-pole regions are doped and annealed, to form a plurality of N-type diffusion regions in the exposed portions of the P-pole regions. A metal layer is formed which fills the contact windows. The metal layer is patterned to form a plurality of essentially parallel word lines. A read only memory device is proposed that includes as plurality of essentially parallel P-pole regions are located on a substrate. A plurality of P-type diffusion regions are located under selected portions of respective P-pole regions. A plurality of N-type diffusion regions are located over respective selected portions of the P-pole regions. Each respective N-type diffusion region and associated P-pole region forms a diode.
摘要翻译：形成ROM的方法包括在P型衬底上形成衬垫氧化层，在衬垫氧化层上形成氮化硅层并对氮化硅层进行构图。在P型衬底中形成N阱，其中一些氮化硅层在N阱之上。在衬底上形成场氧化物层。去除氮化硅层。使用第一P型离子掺杂N阱以形成多个基本上平行的P极区域。在场氧化物层上形成绝缘层。在绝缘层内形成多个接触窗，露出一部分P极区域。 N阱被掺杂并退火，以在P极区域的暴露部分之下形成多个P型扩散区域。 P极区域被掺杂并退火，以在P极区域的暴露部分中形成多个N型扩散区域。形成填充接触窗的金属层。将金属层图案化以形成多个基本平行的字线。提出了一种只读存储器件，其包括多个基本上平行的P极区域位于衬底上。多个P型扩散区域位于相应P极区域的选定部分的下方。多个N型扩散区域位于P极区域的各个选定部分上。每个相应的N型扩散区和相关的P极区形成二极管。

10. 发明授权

US5554562A Advanced isolation scheme for deep submicron technology 失效
公开(公告)号：US5554562A
公开(公告)日：1996-09-10
申请号：US417572
申请日：1995-04-06
申请人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Frederick N. Hause
发明人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/20 , H01L21/762
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76294
摘要： An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

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