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1. 发明授权

US06365943B1 High density integrated circuit 有权
公开(公告)号：US06365943B1
公开(公告)日：2002-04-02
申请号：US09157644
申请日：1998-09-21
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L2976
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.

2. 发明授权

US6104064A Asymmetrical transistor structure 有权
标题翻译：不对称晶体管结构
公开(公告)号：US6104064A
公开(公告)日：2000-08-15
申请号：US306508
申请日：1999-05-06
申请人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
发明人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28211 , H01L21/28176 , H01L29/66659 , H01L29/7835
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

3. 发明授权

US5770483A Multi-level transistor fabrication method with high performance drain-to-gate connection 失效
标题翻译：具有高性能漏极 - 栅极连接的多电平晶体管制造方法
公开(公告)号：US5770483A
公开(公告)日：1998-06-23
申请号：US729795
申请日：1996-10-08
申请人： Daniel Kadosh , Mark I. Gardner , Fred N. Hause
发明人： Daniel Kadosh , Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/768 , H01L21/822 , H01L23/48 , H01L27/06 , H01L21/00 , H01L21/84
CPC分类号： H01L27/0688 , H01L21/8221 , H01L23/485 , H01L23/535 , H01L2924/0002
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between the drain region of an upper level transistor to the gate of a lower level transistor so as to effect a direct coupling between the output of one transistor to the input of another. Direct coupling in this fashion affords a lower propagation delay and therefore achieves the benefit of a higher performance, faster switching circuit.
摘要翻译：提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。多级制造工艺不仅增加了整体电路密度，而且重点放在了在不同层次的器件之间的互连上。因此，引入了高性能互连，由此在一个晶体管级内的特征之间使互连尽可能短以达到另一晶体管级内的特征。互连采用直接在上级晶体管的漏极区域到低级晶体管的栅极之间的通孔，以便实现一个晶体管的输出与另一晶体管的输入之间的直接耦合。以这种方式的直接耦合提供较低的传播延迟，从而实现更高性能，更快速的开关电路的益处。

4. 发明授权

US6046471A Ultra shallow junction depth transistors 失效
标题翻译：超浅结深度晶体管
公开(公告)号：US6046471A
公开(公告)日：2000-04-04
申请号：US744405
申请日：1996-11-07
申请人： Mark I. Gardner , Fred N. Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred N. Hause , Daniel Kadosh
IPC分类号： H01L21/265 , H01L21/336 , H01L31/119
CPC分类号： H01L29/66575 , H01L21/2652
摘要： A shallow junction MOS transistor comprising a semiconductor substrate having an upper region that includes a first and a second lightly doped region laterally displaced on either side of the channel region. The first and second lightly doped regions extend to a junction depth below the upper surface of the semiconductor substrate. A first and a second lightly doped impurity distribution are located within the first and second source/drain regions of the semiconductor substrate. The shallow junction transistor further includes a gate dielectric formed on an upper surface of the channel region of the semiconductor substrate. A conductive gate that includes a first and a second sidewall is formed on the gate dielectric. A gate insulator is formed in contact with the first and second sidewalls of the conductive gate. First and second source/drain structures are formed above the upper surface of the semiconductor substrate. The first and second source/drain structures are laterally displaced over the first and second lightly doped regions of the semiconductor substrate.
摘要翻译：一种浅结MOS晶体管，包括具有上部区域的半导体衬底，所述上部区域包括在沟道区域的任一侧上横向移位的第一和第二轻掺杂区域。第一和第二轻掺杂区域延伸到半导体衬底的上表面下方的结深度。第一和第二轻掺杂杂质分布位于半导体衬底的第一和第二源极/漏极区域内。浅结晶体管还包括形成在半导体衬底的沟道区的上表面上的栅极电介质。包括第一和第二侧壁的导电栅极形成在栅极电介质上。栅极绝缘体形成为与导电栅极的第一和第二侧壁接触。第一和第二源极/漏极结构形成在半导体衬底的上表面之上。第一和第二源极/漏极结构在半导体衬底的第一和第二轻掺杂区域上横向移位。

5. 发明授权

US5994779A Semiconductor fabrication employing a spacer metallization technique 失效
标题翻译：采用间隔金属化技术的半导体制造
公开(公告)号：US5994779A
公开(公告)日：1999-11-30
申请号：US850253
申请日：1997-05-02
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/528
CPC分类号： H01L21/76885 , H01L21/76838 , H01L23/5283 , H01L2924/0002
摘要： An integrated circuit fabrication process is provided in which an interconnect having a least one vertical sidewall surface is formed. The interconnect thusly formed allows for higher packing density within the ensuring integrated circuit since the interconnect requires less space to accommodate the same current density as an interconnect having sloped (i.e., non-vertical) sidewall surfaces. A semiconductor topography is provided which includes transistors arranged upon and within a silicon-based substrate. A first interlevel dielectric is deposited across the semiconductor topography, and portions of the dielectric are removed to form vias to select portions of the transistors. Conductive plugs are formed exclusively within the vias. An insulating material patterned with vertical sidewall surfaces is then formed across the first interlevel dielectric and a portion of the plugs. The insulating material is then patterned. Conductive material is then deposited across the patterned insulating material, the plug upper surfaces, and the first interlevel dielectric. A portion of the conductive material is anisotropically removed to form interconnects which are laterally adjacent to the sidewall surfaces of the insulating material. Each interconnect includes two surfaces, one of which is vertical to the underlying topography and the other of which extends a distance from the fist surface and links with an upper region of the surface in an arcuate pattern. The first lateral surface of the interconnect is directly adjacent to a sidewall surface of the insulating material and is therefore intended to be vertical. The second lateral surface extends a distance from the first lateral surface, constrained the limitations of deposition and not lithography.
摘要翻译：提供一种集成电路制造工艺，其中形成具有至少一个垂直侧壁表面的互连。这样形成的互连允许在确保集成电路内的更高的封装密度，因为互连需要更少的空间以适应与具有倾斜（即，非垂直）侧壁表面的互连件相同的电流密度。提供半导体形貌，其包括布置在硅基衬底上和内部的晶体管。第一层间电介质淀积跨半导体形貌，去除电介质的部分以形成通孔以选择晶体管的部分。导电插头仅在通孔内形成。然后，跨越第一层间电介质和一部分插塞形成图案化有垂直侧壁表面的绝缘材料。然后将绝缘材料图案化。导电材料然后沉积在图案化的绝缘材料，插塞上表面和第一层间电介质上。导电材料的一部分被各向异性地去除以形成横向邻近绝缘材料的侧壁表面的互连。每个互连包括两个表面，其中一个垂直于下面的地形，另一个表面与第一表面延伸一段距离，并以弓形图案与表面的上部区域连接。互连的第一侧表面直接邻近绝缘材料的侧壁表面，因此意图是垂直的。第二侧表面从第一侧表面延伸一段距离，限制了沉积的限制，而不是光刻。

6. 发明授权

US5851883A High density integrated circuit process 失效
标题翻译：高密度集成电路工艺
公开(公告)号：US5851883A
公开(公告)日：1998-12-22
申请号：US844975
申请日：1997-04-23
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.
摘要翻译：在包括硅基层的半导体衬底的上表面上形成介电层的半导体工艺。此后，在电介质层的上表面上形成上硅层。然后对电介质层和上硅层进行构图以在基底硅层的上表面上形成第一和第二硅 - 电介质叠层。第一和第二硅 - 电介质堆叠在硅衬底的沟道区域的任一侧上横向移位，并且每个包括近侧壁和远侧壁。近侧侧壁与通道区域的各个边界大致重合。此后，分别在第一和第二硅 - 电介质堆叠的近侧和远侧壁上形成近端和远端间隔结构。然后在硅基层的暴露部分上在基底硅层的沟道区上形成栅极电介质层。然后选择性地去除位于基底硅层的相应源极/漏极区域之上的第一和第二硅 - 电介质叠层的部分。然后沉积硅以填充由所选择的堆叠移除产生的第一和第二空隙。硅沉积还在沟道区域上填充栅极电介质上方的硅栅极区域。此后，将杂质分布引入沉积的硅中。沉积的硅然后被平坦化以物理地隔离第一和第二空隙内的栅极区域内的硅，从而形成包括硅栅极结构和第一和第二源极/漏极结构的晶体管。

7. 发明授权

US06323561B1 Spacer formation for precise salicide formation 失效
标题翻译：间歇形成精确的自杀化合物形成
公开(公告)号：US06323561B1
公开(公告)日：2001-11-27
申请号：US08987455
申请日：1997-12-09
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L27088
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： The formation of a spacer for precise salicide formation is disclosed. In one embodiment, a method includes four steps. In the first step, at least one first spacer is formed, where each spacer is adjacent to an edge of a gate on a substrate and has a triangular geometry. In the second step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer. In the third step, at least one second spacer is formed, where each second spacer overlaps a corresponding first spacer. In the fourth step, a metal silicide within the substrate is formed immediately adjacent to each second spacer.
摘要翻译：公开了形成用于精确的自对准硅化物形成的间隔物。在一个实施例中，一种方法包括四个步骤。在第一步骤中，形成至少一个第一间隔物，其中每个间隔物邻近衬底上的栅极的边缘并且具有三角形几何形状。在第二步骤中，施加离子注入以在每个间隔物下面的衬底内形成渐变的轻掺杂区域，该区域对应于间隔物的三角形几何形状。在第三步骤中，形成至少一个第二间隔物，其中每个第二间隔物与相应的第一间隔物重叠。在第四步骤中，衬底内的金属硅化物紧邻每个第二间隔物形成。

8. 发明授权

US6121631A Test structure to determine the effect of LDD length upon transistor performance 失效
标题翻译：测试结构，以确定LDD长度对晶体管性能的影响
公开(公告)号：US6121631A
公开(公告)日：2000-09-19
申请号：US267444
申请日：1999-03-12
申请人： Mark I Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L23/544 , H01L29/78 , H01L23/58 , H01L27/088 , H01L31/119
CPC分类号： H01L29/6659 , H01L22/34 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , Y10S257/90
摘要： The present invention advantageously provides a method for forming a test structure for determining how LDD length of a transistor affects transistor characteristics. In one embodiment, a first polysilicon gate conductor is provided which is laterally spaced from a second polysilicon gate conductor. The gate conductors are each disposed upon a gate oxide lying above a silicon-based substrate. An LDD implant is forwarded into exposed regions of the substrate to form LDD areas within the substrate adjacent to the gate conductors. A first spacer material is then formed upon sidewall surfaces of both gate conductors to a first pre-defined thickness. Source/drain regions are formed exclusively within the substrate a spaced distance from the first gate conductor, the spaced distance being dictated by the first pre-defined thickness. A second spacer material is formed laterally adjacent to the first spacer material to a second pre-defined distance. Source/drain regions are then formed within the substrate a spaced distance from the second gate conductor, the spaced distance being dictated by the second predefined thickness. The resulting transistors have a mutual source/drain region between them. More transistors may also be fabricated in a similar manner.
摘要翻译：本发明有利地提供了一种用于形成用于确定晶体管的LDD长度如何影响晶体管特性的测试结构的方法。在一个实施例中，提供了与第二多晶硅栅极导体横向间隔开的第一多晶硅栅极导体。栅极导体各自设置在位于硅基衬底之上的栅极氧化物上。将LDD植入物转移到衬底的暴露区域中，以在邻近栅极导体的衬底内形成LDD区域。然后将第一间隔物材料形成在两个栅极导体的侧壁表面上至第一预定义的厚度。源极/漏极区域仅在衬底内形成与第一栅极导体间隔开的距离，间隔距离由第一预定义厚度决定。第二间隔物材料横向地邻近第一间隔物材料形成为第二预定距离。源极/漏极区域然后在衬底内形成与第二栅极导体间隔开的距离，间隔距离由第二预定厚度决定。所得的晶体管在它们之间具有相互的源极/漏极区域。也可以以类似的方式制造更多的晶体管。

9. 发明授权

US6117739A Semiconductor device with layered doped regions and methods of manufacture 有权
标题翻译：具有分层掺杂区域的半导体器件和制造方法
公开(公告)号：US6117739A
公开(公告)日：2000-09-12
申请号：US166000
申请日：1998-10-02
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/266 , H01L21/336 , H01L29/10 , H01L29/49
CPC分类号： H01L29/66583 , H01L21/266 , H01L29/1083 , H01L29/4966 , H01L29/66537
摘要： A semiconductor device can be formed with active regions disposed in a substrate adjacent to a gate electrode and a doped region, of the same conductivity type as the active regions, embedded beneath the channel region defined by the active regions. In one embodiment, a patterned masking layer having at least one opening is formed over the substrate. A dopant material is implanted into the substrate using the masking layer to form active regions adjacent to the opening and an embedded doped region that is between and spaced apart from the active regions and is deeper in the substrate then the active regions. In addition or alternatively, spacer structures can be formed on the gate electrode by forming a conformal dielectric layer along a bottom surface and at least one sidewall of the opening and forming a gate electrode in the opening over the dielectric layer. The masking layer is then removed to leave the dielectric layer between the gate electrode and the substrate and as spacer structures on the sidewalls of the gate electrode.
摘要翻译：可以形成半导体器件，该有源区域设置在与由栅极电极相邻的衬底中的有源区域和与有源区域相同的导电类型的掺杂区域，嵌入在由有源区域限定的沟道区域的下面。在一个实施例中，在衬底上形成具有至少一个开口的图案化掩模层。使用掩模层将掺杂剂材料注入到衬底中以形成与开口相邻的有源区和位于有源区之间并且与有源区间隔开的嵌入的掺杂区，并且在衬底中更深的是有源区。另外或替代地，可以通过沿着底表面和开口的至少一个侧壁形成保形电介质层并在电介质层上的开口中形成栅电极，在栅电极上形成间隔结构。然后去除掩模层以在栅电极和衬底之间留下介电层，并且作为栅电极的侧壁上的间隔结构。

10. 发明授权

US6087249A Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation 有权
标题翻译：晶体管制造工艺采用公共室进行栅极氧化和栅极导体的形成
公开(公告)号：US6087249A
公开(公告)日：2000-07-11
申请号：US151075
申请日：1998-09-10
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： C23C16/40 , C23C16/452 , H01L21/28 , H01L21/314 , H01L29/51 , H01L21/3205
CPC分类号： H01L21/28202 , C23C16/402 , C23C16/452 , H01L21/28017 , H01L21/28035 , H01L21/3145 , H01L29/513 , H01L29/518 , H01L21/28185 , Y10S438/907 , Y10S438/908
摘要： An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber. The initial semiconductor topography includes a silicon substrate having isolation regions disposed within its upper surface. The semiconductor topography may include an defined region, or well, doped opposite the substrate. The semiconductor topography is first placed in the common chamber. A separate chamber is operably placed gaseous communication with the common chamber. A plasma is created within the separate chamber, causing nitrogen, silicon, and oxygen containing compounds therein to form ions, molecular fragments, and excited molecules which are transported to the common chamber. The ions, molecular fragments, and excited molecules react and bombard the surface of the semiconductor topography to form an oxide layer thereon. The oxide layer is incorporated with nitrogen atoms which act as barrier atoms. Polysilicon is then deposited upon the oxide layer by CVD within the common chamber. The semiconductor topography is never exposed to ambient conditions outside the common chamber during and between the plasma oxide formation and the polysilicon deposition steps. Preventing ingress of outside ambient helps minimize contamination from entering the oxide. During the polysilicon deposition, dopant atoms are forwarded and become entrained within the polysilicon. The barrier atoms within the deposited oxide helps minimize dopant atoms from passing through the oxide and entering the channel below the oxide.
摘要翻译：提供一种集成电路晶体管，其具有栅极氧化物和布置在半导体形貌上的栅极导体，栅极氧化物和栅极导体形成在公共室内。初始半导体形貌包括具有设置在其上表面内的隔离区的硅衬底。半导体形貌可以包括与衬底相对掺杂的限定区域或阱。首先将半导体形貌放置在公共室中。独立的腔室可操作地与公共腔室气体连通。在分离的室内产生等离子体，在其中产生氮，硅和含氧化合物，以形成被输送到公共室的离子，分子片段和被激发的分子。离子，分子片段和激发的分子反应并轰击半导体形貌的表面以在其上形成氧化物层。氧化物层与作为阻挡原子的氮原子结合。然后通过CVD在公共室内将多晶硅沉积在氧化物层上。在等离子体氧化物形成和多晶硅沉积步骤期间和之间，半导体形貌从未暴露于公共室外的环境条件。防止外界进入有助于最大限度地减少进入氧化物的污染。在多晶硅沉积期间，掺杂剂原子被转移并被夹带在多晶硅内。沉积的氧化物内的阻挡原子有助于最小化掺杂剂原子通过氧化物并进入氧化物下方的通道。

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