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1. 发明授权

US07871469B2 Method for fabricating waveguides 失效
标题翻译：制造波导的方法
公开(公告)号：US07871469B2
公开(公告)日：2011-01-18
申请号：US10867591
申请日：2004-06-14
申请人： Dan Maydan , Arkadii V. Samoilov
发明人： Dan Maydan , Arkadii V. Samoilov
IPC分类号： C30B21/02
CPC分类号： G02B6/132 , G02B2006/12095 , G02B2006/121 , Y10T117/10
摘要： A method of forming a planar waveguide structure, comprising forming a first graded layer on a substrate, wherein the first graded layer comprises a first and a second optical material, wherein the concentration of the first optical material increases with the height of the first graded layer; forming a second graded layer on the first graded layer, the second graded layer comprising the first and second optical materials wherein the concentration of the first optical material decreases with the height of the second graded layer. The method further including forming a uniform layer on the first graded layer, the uniform layer containing first and second optical materials wherein the first optical material concentration is constant.
摘要翻译：一种形成平面波导结构的方法，包括在衬底上形成第一渐变层，其中所述第一渐变层包括第一和第二光学材料，其中所述第一光学材料的浓度随着所述第一渐变层的高度而增加 ; 在所述第一渐变层上形成第二渐变层，所述第二渐变层包括所述第一和第二光学材料，其中所述第一光学材料的浓度随着所述第二渐变层的高度而降低。该方法还包括在第一梯度层上形成均匀的层，所述均匀层包含第一和第二光学材料，其中第一光学材料浓度恒定。

2. 发明授权

US06770134B2 Method for fabricating waveguides 失效
公开(公告)号：US06770134B2
公开(公告)日：2004-08-03
申请号：US09866172
申请日：2001-05-24
申请人： Dan Maydan , Arkadii V. Samoilov
发明人： Dan Maydan , Arkadii V. Samoilov
IPC分类号： C30B2304
CPC分类号： G02B6/132 , G02B2006/12095 , G02B2006/121 , Y10T117/10
摘要： A method of forming a planar waveguide structure, comprising forming a first graded layer on a substrate, wherein the first graded layer comprises a first and a second optical material, wherein the concentration of the first optical material increases with the height of the first graded layer; forming a second graded layer on the first graded layer, the second graded layer comprising the first and second optical materials wherein the concentration of the first optical material decreases with the height of the second graded layer. The method further including forming a uniform layer on the first graded layer, the uniform layer containing first and second optical materials wherein the first optical material concentration is constant.

3. 发明申请

US20070080414A1 Optical ready substrates 审中-公开
标题翻译：光学就绪基板
公开(公告)号：US20070080414A1
公开(公告)日：2007-04-12
申请号：US11522856
申请日：2006-09-18
申请人： Claes Bjorkman , Lawrence West , Dan Maydan , Samuel Broydo
发明人： Claes Bjorkman , Lawrence West , Dan Maydan , Samuel Broydo
IPC分类号： H01L31/0232
CPC分类号： G02B6/43 , G02B6/12 , G02B6/12004 , G02B6/30 , G02B6/4204 , G02B6/4214 , G02B6/4245 , G02B6/4257 , G02B6/4274 , G02B6/4283 , H01L21/84 , H01L27/1203
摘要： An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.
摘要翻译：一种制造方法，包括由第一半导体层制成的光学就绪衬底，在第一半导体层的顶部上的绝缘层和在绝缘层的顶部上的第二半导体层，其中第二半导体层具有顶表面和横向分为包括第一区域和第二区域的两个区域，第一区域的顶表面具有足以允许在其中形成微电子电路的质量，并且第二区域包括其中形成的光信号分配电路，所述光信号分配电路由互连的半导体光子元件组成并且被设计成向要在第二半导体层的第一区域中制造的微电子电路提供信号。

4. 发明授权

US06610354B2 Plasma display panel with a low k dielectric layer 失效
公开(公告)号：US06610354B2
公开(公告)日：2003-08-26
申请号：US09886174
申请日：2001-06-18
申请人： Kam S. Law , Quanyuan Shang , Takako Takehara , Taekyung Won , William R. Harshbarger , Dan Maydan
发明人： Kam S. Law , Quanyuan Shang , Takako Takehara , Taekyung Won , William R. Harshbarger , Dan Maydan
IPC分类号： C23C1640
CPC分类号： H01J11/38 , H01J11/12
摘要： A plasma display panel including a low k dielectric layer. In one embodiment, the dielectric layer is comprises a fluorine-doped silicon oxide layer such as an SiOF layer. In another embodiment, the dielectric layer comprises a Black Diamond™ layer. In certain embodiments, a capping layer such as SiN or SiON is deposited over the dielectric layer.

5. 发明授权

US06514850B2 Interface with dielectric layer and method of making 失效
公开(公告)号：US06514850B2
公开(公告)日：2003-02-04
申请号：US09775010
申请日：2001-01-31
申请人： Li-Qun Xia , Huong Thanh Nguyen , Ellie Yieh , Dan Maydan
发明人： Li-Qun Xia , Huong Thanh Nguyen , Ellie Yieh , Dan Maydan
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/02115 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/3105 , H01L21/31116 , H01L21/3144 , H01L21/76801 , H01L21/76807 , H01L21/76826
摘要： Methods of forming an interface in a dielectric material to act as an indicator for terminating an etching process, and products produced thereby.

6. 发明授权

US6055927A Apparatus and method for white powder reduction in silicon nitride deposition using remote plasma source cleaning technology 失效
公开(公告)号：US6055927A
公开(公告)日：2000-05-02
申请号：US782169
申请日：1997-01-14
申请人： Quanyuan Shang , Robert McCormick Robertson , Kam S. Law , Dan Maydan
发明人： Quanyuan Shang , Robert McCormick Robertson , Kam S. Law , Dan Maydan
IPC分类号： B08B7/00 , C23C16/42 , C23C16/44 , C23C16/52 , H01L21/205 , H01L21/3065 , H01L21/31 , C23C16/00
CPC分类号： C23C16/4405
摘要： An apparatus and method for reducing the production of white powder in a process chamber used for depositing silicon nitride. Steps of the method include heating at least a portion of a wall of the process chamber; providing a liner covering a substantial portion of a wall of the process chamber; providing a remote chamber connected to the interior of the process chamber; causing a plasma of cleaning gas in the remote chamber; and flowing a portion of the plasma of cleaning gas into the process chamber. The apparatus includes a deposition chamber having walls; means for heating the walls, the means thermally coupled to the walls; a liner covering a substantial portion of the walls; a remote chamber disposed outside of the chamber; an activation source adapted to deliver energy into the remote chamber; a first conduit for flowing a precursor gas from a remote gas supply into the remote chamber where it is activated by the activation source to form a reactive species; and a second conduit for flowing the reactive species from the remote chamber into the deposition chamber.

7. 发明授权

US6040022A PECVD of compounds of silicon from silane and nitrogen 失效
标题翻译：来自硅烷和氮的硅化合物的PECVD
公开(公告)号：US6040022A
公开(公告)日：2000-03-21
申请号：US59734
申请日：1998-04-14
申请人： Mei Chang , David N. K. Wang , John M. White , Dan Maydan
发明人： Mei Chang , David N. K. Wang , John M. White , Dan Maydan
IPC分类号： C23C16/50 , C23C16/34 , C23C16/44 , C23C16/455 , C23C16/509 , B05D3/06 , C23C16/30
CPC分类号： C23C16/45565 , C23C16/345 , C23C16/455 , C23C16/5096
摘要： An inlet gas manifold for a vacuum deposition chamber incorporates inlet apertures which increase in diameter or cross-section transverse to the direction of gas flow. The aperture configuration increases the dissociation gases such as nitrogen and, thus increases the rate of silicon nitride deposition provided by nitrogen gas chemistry, without requiring the use of reactants such as ammonia. While one could use ammonia in the deposition gas chemistry if desired, the process provides the option of completely eliminating ammonia. The inlet manifold containing the increasing-diameter gas inlet holes provides enhanced control of the process and the deposited film, and is also useful for forming other dielectrics such as silicon oxide and silicon oxynitride. In particular, silicon oxynitride films are characterized by low hydrogen content and by compositional uniformity.
摘要翻译：用于真空沉积室的入口气体歧管包括入口孔，其直径或横截面横向于气体流动方向增加。孔径构造增加了解离气体如氮气，从而增加了由氮气化学提供的氮化硅沉积速率，而不需要使用诸如氨的反应物。虽然如果需要，可以在沉积气体化学中使用氨，该方法提供完全消除氨的选择。包含增加直径的气体入口孔的入口歧管提供对工艺和沉积膜的增强的控制，并且还可用于形成其它电介质，例如氧化硅和氮氧化硅。特别地，氧氮化硅膜的特征在于低氢含量和组成均匀性。

8. 发明授权

US5720818A Conduits for flow of heat transfer fluid to the surface of an electrostatic chuck 失效
公开(公告)号：US5720818A
公开(公告)日：1998-02-24
申请号：US639596
申请日：1996-04-26
申请人： Arik Donde , Dan Maydan , Robert J. Steger , Edwin C. Weldon , Brian Lue , Timothy Dyer
发明人： Arik Donde , Dan Maydan , Robert J. Steger , Edwin C. Weldon , Brian Lue , Timothy Dyer
IPC分类号： B23Q3/15 , C23C16/458 , H01L21/683 , C23C16/00
CPC分类号： H01J37/321 , C23C16/4586 , H01L21/6831 , H01L21/6833 , H01J2237/2001 , Y10T29/49002 , Y10T29/49826 , Y10T29/49885
摘要： The present invention discloses a two basic structures (including multiple variations within one of the basic structures) and methods for fabrication of the structures which facilitate the flow of cooling gas or other heat transfer fluid to the surface of an electrostatic chuck. The basic structures address both the problem of breakdown of a heat transfer gas in an RF plasma environment and the problem of arcing between a semiconductor substrate and the conductive pedestal portion of the electrostatic chuck in such an RF plasma environment.

9. 发明授权

US5292393A Multichamber integrated process system 失效
标题翻译：多室综合过程系统
公开(公告)号：US5292393A
公开(公告)日：1994-03-08
申请号：US808786
申请日：1991-12-16
申请人： Dan Maydan , Sasson Somekh , David N. Wang , David Cheng , Masato Toshima , Isaac Harari , Peter D. Hoppe
发明人： Dan Maydan , Sasson Somekh , David N. Wang , David Cheng , Masato Toshima , Isaac Harari , Peter D. Hoppe
IPC分类号： H01L21/00 , C23C16/00 , B65G1/06
CPC分类号： H01L21/67167 , H01L21/67201
摘要： An integrated modular multiple chamber vacuum processing system is disclosed. The system includes a load lock, may include an external cassette elevator, and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load lock chamber. A robot is mounted within the load lock and utilizes a concentric shaft drive system connected to an end effector via a dual four-bar link mechanism for imparting selected R-.theta. movement to the blade to load and unload wafers at the external elevator, internal elevator and individual process chambers. The system is uniquely adapted for enabling various types of IC processing including etch, deposition, sputtering and rapid thermal annealing chambers, thereby providing the opportunity for multiple step, sequential processing using different processes.
摘要翻译：公开了一种集成的模块化多室真空处理系统。该系统包括一个加载锁定，可以包括一个外部盒式电梯和一个内部装载锁定晶片升降机，并且还包括围绕负载锁的周边的站，用于将一个，两个或几个真空处理室连接到负载锁定室。机器人被安装在装载锁中，并且利用通过双重四杆连杆机构连接到端部执行器的同心轴驱动系统，用于将选定的R（θ）运动传递到叶片以在外部升降机上加载和卸载晶片，内部电梯和各个处理室。该系统独特地适用于实现各种类型的IC处理，包括蚀刻，沉积，溅射和快速热退火室，从而为使用不同工艺的多步骤顺序处理提供了机会。

10. 发明授权

US5204288A Method for planarizing an integrated circuit structure using low melting inorganic material 失效
标题翻译：使用低熔点无机材料平面化集成电路结构的方法
公开(公告)号：US5204288A
公开(公告)日：1993-04-20
申请号：US845544
申请日：1992-03-04
申请人： Jeffrey Marks , Kam S. Law , David N. Wang , Dan Maydan
发明人： Jeffrey Marks , Kam S. Law , David N. Wang , Dan Maydan
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L23/31
CPC分类号： H01L21/3105 , H01L21/31055 , H01L21/31604 , H01L21/76819 , H01L23/3157 , H01L2924/0002 , Y10S148/133 , Y10S438/913
摘要： A planarizing process for planarizing an integrated circuit structure in a CVD apparatus is disclosed using a low melting inorganic planarizing material which comprises flowing white depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon, then dry etching the low melting inorganic planarizing layer to planarize the structure, and then depositing a further layer of an insulating material to encapsulate any remaining portions of the low melting glass planarizing layer which may be hygroscopic. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are all carried out without removing the integrated circuit structure from the apparatus. In a particularly preferred embodiment, all of the steps are carried out in the same chamber of the apparatus. An additional etching step may be carried out after depositing the first insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.
摘要翻译：公开了使用低熔点无机平面化材料来平坦化CVD装置中的集成电路结构的平面化工艺，该无机平面化材料包括使诸如氧化硼玻璃之类的低熔点无机平面化层在诸如氧化物硅，然后干法蚀刻低熔点无机平面化层以使结构平坦化，然后沉积另外的绝缘材料层以封装可能是吸湿性的低熔点玻璃平坦化层的任何剩余部分。该方法消除了对通常在真空装置外进行的有机基平坦化层的应用的独立涂布，干燥和固化步骤的需要。在优选实施例中，沉积步骤和蚀刻步骤全部进行而不从集成电路结构从设备中移除。在特别优选的实施例中，所有步骤在装置的相同腔室中进行。在沉积第一绝缘层之后并且在沉积平坦化层以去除在绝缘层中形成的任何空隙之前，可以进行另外的蚀刻步骤。

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