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    • 5. 发明授权
    • Network interface architecture for a packet switch communication system
    • 分组交换机通信系统的网络接口架构
    • US5524007A
    • 1996-06-04
    • US165718
    • 1993-12-13
    • Richard E. WhiteDale R. BuchholzThomas A. FreeburgLisa B. Johanson
    • Richard E. WhiteDale R. BuchholzThomas A. FreeburgLisa B. Johanson
    • G06F13/42H04B1/16H04B1/38H04L12/56H04L12/64H04M1/73H04W92/02H04L12/40
    • H04W92/02G06F13/423H04B1/1615H04B1/38H04J3/0697H04L12/56H04L12/64H04L12/6402H04W52/0245
    • An improved network interface architecture for a packet switch provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (NI) provides a mechanism (the NI-Bus) of passing all packets through the Network Interface or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The network interface architecture, according to the invention, allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as, for example, 40 Mbps. It also allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
    • 用于分组交换机的改进的网络接口架构使用公共分组结构在单个交换机中提供语音和数据的组合。 它允许基于系统加载的带宽的动态分配。 这不仅包括帧的语音或数据区域内的带宽,还包括语音和数据部分之间的带宽。 网络接口(NI)提供了通过网络接口传递所有数据包或允许数据包设备在彼此之间直接传输数据包的机制(NI-Bus)。 带宽分配可以容易地改变,因为控制和数据存储器彼此同步。 根据本发明的网络接口架构允许数据分组和带宽分配的控制由单个交换设备控制。 它同步数据的传输和总线带宽的分配。 可以以非常高的比特率(例如40Mbps)来控制分组设备的控制。 它还允许数据包设备直接传输数据包。 它允许通过使用NI基本寄存器轻松重新分配带宽。
    • 7. 发明授权
    • Signal communication method and apparatus
    • 信号通信方法及装置
    • US5471471A
    • 1995-11-28
    • US817023
    • 1992-01-03
    • Thomas A. FreeburgDennis E. BurkePaul Odlyzko
    • Thomas A. FreeburgDennis E. BurkePaul Odlyzko
    • H04L12/40H04W88/06H04B7/00H04J3/12
    • H04W88/06
    • A communications system having a plurality of different radio-types (528, 530 and 532) when integrated into a single node or control module (500) provides communications with a plurality of different end users (502, 506 and 508) having different transmission protocols. The steps involved comprise coupling the plurality of communication devices (528, 530 and 532) together via a bus (526) and coupling at least one processing unit (517) to the bus (526). Signals received by RF devices (528, 530 and 532) are communicated onto the bus (526) and processed by the processing unit (517) into processed signals. Processed signals comprise data and control information which are stored in memory (522). Thereafter, the processed signals stored in memory (522) are returned back onto the bus (526) for use by at least one of the plurality of communication devices (528, 530 and 532).
    • 当集成到单个节点或控制模块(500)中时,具有多个不同无线电类型(528,530和532)的通信系统提供与具有不同传输协议的多个不同终端用户(502,506和508)的通信 。 所涉及的步骤包括经由总线(526)将多个通信设备(528,530和532)耦合在一起,并将至少一个处理单元(517)耦合到总线(526)。 由RF设备(528,530和532)接收的信号被传送到总线(526)上,由处理单元(517)处理成处理的信号。 处理信号包括存储在存储器(522)中的数据和控制信息。 此后,存储在存储器(522)中的已处理信号被返回到总线(526)上,供多个通信设备(528,530和532)中的至少一个使用。
    • 10. 发明授权
    • Frequency locked-loop using a microcontroller as a comparator
    • 使用微控制器作为比较器的锁相环
    • US5705955A
    • 1998-01-06
    • US576520
    • 1995-12-21
    • Thomas A. FreeburgJohn LeyAnne M. PearceGary SchulzPaul Odlyzko
    • Thomas A. FreeburgJohn LeyAnne M. PearceGary SchulzPaul Odlyzko
    • H03L7/06H03L7/085H03C3/09H04L27/12
    • H03L7/06
    • A frequency-locked loop (100) employs a controllable oscillator (102) for generating an output signal having a frequency, optional sampler (104), coupled to oscillator (102), for sampling the frequency of the output signal, a divider (106), coupled to optional sampling circuit (104), for dividing the output signal frequency to generate a prescaled signal and a microprocessor (108), coupled between the divider 106 and oscillator (102), for comparing the prescaled signal to a reference signal and generating a control signal for correcting frequency shifts based upon the comparison. The control signal generated by microprocessor (108) is non-continuous. During that time when microprocessor (108) generates no control signals, power is removed from various frequency-locked loop circuitry.
    • 频率锁定环路(100)采用可控振荡器(102),用于产生具有耦合到振荡器(102)的频率可选取样器(104)的输出信号,用于对输出信号的频率进行采样,分频器(106) ),耦合到可选采样电路(104),用于分频输出信号频率以产生预定信号;耦合在分频器106和振荡器(102)之间的微处理器(108)),用于将预定信号与参考信号进行比较;以及 根据比较产生用于校正频移的控制信号。 由微处理器(108)产生的控制信号是不连续的。 在微处理器(108)不产生控制信号的那段时间内,从各种锁频环路电路去除功率。