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1. 发明授权

US5878094A Noise detection and delay receiver system 失效
标题翻译：噪声检测和延迟接收系统
公开(公告)号：US5878094A
公开(公告)日：1999-03-02
申请号：US879486
申请日：1997-06-10
申请人： Edward J. Nowak , Dale E. Pontius , Michael A. Roberge , Minh H. Tong
发明人： Edward J. Nowak , Dale E. Pontius , Michael A. Roberge , Minh H. Tong
IPC分类号： H03K5/1252 , H03K17/16 , H04B1/10
CPC分类号： H03K17/162 , H03K5/1252
摘要： A noise detection and delay receiver circuit includes a circuit input and output and a plurality of individual receiver circuits connected to the input having trip points which range from a low trip point to a high trip point. Edge detect circuitry and delay circuitry are used to prevent the output from changing back to the previous state for a period of time immediately after it has just changed state. Multiple transitions of the input voltage across the trip points of the individual receivers are used to delay the response until noise has settled out of the input signal.
摘要翻译：噪声检测和延迟接收器电路包括电路输入和输出以及连接到具有从低跳变点到高跳变点的跳变点的输入的多个单独的接收器电路。边缘检测电路和延迟电路用于防止输出在其刚刚改变状态之后立即改变到之前的状态一段时间。使用各个接收器的跳变点之间的输入电压的多次转换来延迟响应，直到噪声已经从输入信号稳定出来。

2. 发明授权

US06327224B1 On-chip method for measuring access time and data-pin spread 失效
标题翻译：用于测量访问时间和数据引脚扩展的片上方法
公开(公告)号：US06327224B1
公开(公告)日：2001-12-04
申请号：US09595632
申请日：2000-06-16
申请人： Geordie Maria Braceras , Harold Pilo , Dale E. Pontius
发明人： Geordie Maria Braceras , Harold Pilo , Dale E. Pontius
IPC分类号： G04F1000
CPC分类号： G01R31/31858 , G11C29/50
摘要： An on-chip I/O timings measurement circuit that improves measurement accuracy compared to conventional external test methods. This circuit guarantees AC timing specifications that are too small for the measurement capabilities of today's high-frequency memory testers. This system in incorporated into the SRAM via the JTAG interface and a JTAG private instruction. A private instruction refers to an unused instruction from the industry-standard public instruction set. Private instructions are usually reserved for the manufacturer, but may be provided to the user as an enhancement to the standard JTAG instruction set.
摘要翻译：一种片上I / O时序测量电路，与传统的外部测试方法相比，可提高测量精度。该电路保证对当今高频记忆体测试仪的测量能力太小的交流定时规格。该系统通过JTAG接口和JTAG专用指令并入SRAM。私有指令是指来自行业标准公共指令集的未使用指令。私有指令通常为制造商保留，但可作为标准JTAG指令集的增强提供给用户。

3. 发明授权

US5519664A Dynamic random access memory persistent page implemented as processor register sets 失效
公开(公告)号：US5519664A
公开(公告)日：1996-05-21
申请号：US450325
申请日：1995-05-25
申请人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
发明人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
IPC分类号： G11C11/401 , G06F1/32 , G06F12/02 , G06F12/08 , G11C5/14 , G11C7/00 , G11C7/10 , G11C11/4096
CPC分类号： G06F1/3275 , G06F1/32 , G06F12/0215 , G06F12/0882 , G06F12/0893 , G11C11/4096 , G11C7/1051 , G11C7/1078 , Y02B60/1225 , Y02B60/1228
摘要： The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

4. 发明授权

US5555528A Dynamic random access memory persistent page implemented as processor register sets 失效
公开(公告)号：US5555528A
公开(公告)日：1996-09-10
申请号：US450324
申请日：1995-05-25
申请人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
发明人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
IPC分类号： G11C11/401 , G06F1/32 , G06F12/02 , G06F12/08 , G11C5/14 , G11C7/00 , G11C7/10 , G11C11/4096
CPC分类号： G06F1/3275 , G06F1/32 , G06F12/0215 , G06F12/0882 , G06F12/0893 , G11C11/4096 , G11C7/1051 , G11C7/1078 , Y02B60/1225 , Y02B60/1228
摘要： The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

5. 发明授权

US5508968A Dynamic random access memory persistent page implemented as processor register sets 失效
标题翻译：作为处理器寄存器集实现的动态随机存取存储器持久页面
公开(公告)号：US5508968A
公开(公告)日：1996-04-16
申请号：US289149
申请日：1994-08-12
申请人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
发明人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
IPC分类号： G11C11/401 , G06F1/32 , G06F12/02 , G06F12/08 , G11C5/14 , G11C7/00 , G11C7/10 , G11C11/4096
CPC分类号： G06F1/3275 , G06F1/32 , G06F12/0215 , G06F12/0882 , G06F12/0893 , G11C11/4096 , G11C7/1051 , G11C7/1078 , Y02B60/1225 , Y02B60/1228
摘要： The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.
摘要翻译：使用位于具有处理器的半导体芯片上的动态随机存取存储器（DRAM）的阵列的读出放大器寄存器（SAR）全部保持为全功率，而不可用的阵列被掉电以节省功率。 DRAM的访问电路允许处理器访问每个SAR的字长段彼此独立，使得SAR用作处理器的读/写高速缓存。

6. 发明授权

US5278800A Memory system and unique memory chip allowing island interlace 失效
标题翻译：内存系统和独特的内存芯片允许岛交错
公开(公告)号：US5278800A
公开(公告)日：1994-01-11
申请号：US786139
申请日：1991-10-31
申请人： Warren W. Grunbok , Billy J. Knowles , William R. Milani , Douglas R. Moran , Dale E. Pontius , Donald W. Price , Robert Tamlyn , Yee-Ming Ting , De Tran , Henry Yeh
发明人： Warren W. Grunbok , Billy J. Knowles , William R. Milani , Douglas R. Moran , Dale E. Pontius , Donald W. Price , Robert Tamlyn , Yee-Ming Ting , De Tran , Henry Yeh
IPC分类号： G06F12/06 , G06F13/16 , G11C8/12 , G11C7/00
CPC分类号： G06F12/06 , G06F13/1657 , G11C8/12
摘要： A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.
摘要翻译：公开了一种存储器系统和独特的存储器芯片，其中芯片上的多个岛可以由单独的岛控制器单独访问，从而可以实现芯片上的多个岛或阵列的并发使用。

7. 发明授权

US08300489B2 Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump 有权
标题翻译：电荷泵系统和方法利用可调输出电荷和汇编系统及方法供电泵使用
公开(公告)号：US08300489B2
公开(公告)日：2012-10-30
申请号：US12686013
申请日：2010-01-12
申请人： John A. Fifield , Thomas M. Maffitt , Dale E. Pontius
发明人： John A. Fifield , Thomas M. Maffitt , Dale E. Pontius
IPC分类号： G11C7/00
CPC分类号： H02M3/07 , G11C5/145 , G11C29/021 , G11C29/028
摘要： Charge pump circuit includes a plurality of boost capacitors. An output charge of the charge pump circuit is adjusted by selecting a number of the boost capacitors at least one of using a digital control word and programming of a wiring level. A method of boosting supply voltage uses a charge pump circuit. The method includes adjusting an output charge of the charge pump circuit by selecting a number of boost capacitors at least one of using a digital control word and by programming of a wiring level.
摘要翻译：电荷泵电路包括多个升压电容器。通过选择多个升压电容器来调整电荷泵电路的输出电荷，至少使用数字控制字和布线电平的编程。提高电源电压的方法使用电荷泵电路。该方法包括通过选择多个升压电容器来调节电荷泵电路的输出电荷，所述升压电容器使用数字控制字和编程布线电平中的至少一个。

8. 发明授权

US06674673B1 Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture 有权
公开(公告)号：US06674673B1
公开(公告)日：2004-01-06
申请号：US10064867
申请日：2002-08-26
申请人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
发明人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C2207/104
摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.

9. 发明授权

US5606269A Non-delay based address transition detector (ATD) 失效
标题翻译：基于非延迟的地址转换检测器（ATD）
公开(公告)号：US5606269A
公开(公告)日：1997-02-25
申请号：US548651
申请日：1995-10-26
申请人： Dale E. Pontius , Robert Tamlyn
发明人： Dale E. Pontius , Robert Tamlyn
IPC分类号： H03K5/1534 , H03K19/003
CPC分类号： H03K5/1534
摘要： A circuit for detecting an input signal, the circuit having an input node and an output node, includes a first latch having a set input coupled to the input node, for detecting falling transitions at the input node. A second latch having a set input coupled to the input node, detects rising transitions at the input node. A first logic device, responsive to outputs of the first and second latches, detects that an input signal has been received at both the first and second latches. A second logic device, responsive to a complement output of both the first and second latches, resets both the first and second latches.
摘要翻译：用于检测输入信号的电路，具有输入节点和输出节点的电路包括具有耦合到输入节点的设置输入的第一锁存器，用于检测输入节点处的下降转换。具有耦合到输入节点的设置输入的第二锁存器检测输入节点处的上升转变。响应于第一和第二锁存器的输出的第一逻辑器件检测到在第一和第二锁存器都已经接收到输入信号。响应于第一和第二锁存器的补码输出的第二逻辑器件复位第一和第二锁存器。

10. 发明授权

US5545978A Bandgap reference generator having regulation and kick-start circuits 失效
标题翻译：带隙参考发生器具有调节和启动电路
公开(公告)号：US5545978A
公开(公告)日：1996-08-13
申请号：US266281
申请日：1994-06-27
申请人： Dale E. Pontius
发明人： Dale E. Pontius
IPC分类号： G05F3/30 , G05F3/24 , G05F3/16
CPC分类号： G05F3/24
摘要： A bandgap reference generator providing a reference voltage V.sub.R from a power supply voltage V.sub.DD. The bandgap reference generator includes a bandgap reference circuit and a voltage regulation circuit coupled thereto. The voltage regulation circuit operates to supply power to the bandgap reference circuit such that the voltages at a first internal control node and a second internal control node are equal, wherein the first internal control node and the second internal control node are disposed on different current paths within the bandgap reference circuit. By equalizing voltages at these internal control nodes, device stress within the bandgap reference circuit is reduced. Kick-start circuits for the voltage regulation circuit and the bandgap reference circuit are also included within the bandgap reference generator. In addition, output stage processing can be incorporated to transform an outputted reference voltage V.sub.R from a low stress operating point to a desired reference voltage V.sub.REF.
摘要翻译：带隙参考发生器，从电源电压VDD提供参考电压VR。带隙参考发生器包括带隙参考电路和与其耦合的电压调节电路。电压调节电路用于向带隙基准电路供电，使得第一内部控制节点和第二内部控制节点处的电压相等，其中第一内部控制节点和第二内部控制节点设置在不同的电流路径上在带隙参考电路内。通过均衡这些内部控制节点处的电压，减小了带隙参考电路内的器件应力。用于电压调节电路和带隙参考电路的启动电路也包括在带隙参考发生器内。此外，可以并入输出级处理，以将输出的参考电压VR从低应力工作点变换为期望的参考电压VREF。

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