专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06815721B2 Diamond semiconductor and diamond semiconductor light-emitting device that uses the semiconductor 失效
公开(公告)号：US06815721B2
公开(公告)日：2004-11-09
申请号：US10793798
申请日：2004-03-08
申请人： Hideyo Okushi , Hideyuki Watanabe , Daisuke Takeuchi , Koji Kajimura
发明人： Hideyo Okushi , Hideyuki Watanabe , Daisuke Takeuchi , Koji Kajimura
IPC分类号： H01L310312
CPC分类号： H01L33/34 , H01L21/0405 , H01S5/32 , H01S5/3228
摘要： A diamond semiconductor has an exciton light-emission intensity characteristic that varies nonlinearly.

2. 发明授权

US06727171B2 Diamond pn junction diode and method for the fabrication thereof 失效
标题翻译：金刚石pn结二极管及其制造方法
公开(公告)号：US06727171B2
公开(公告)日：2004-04-27
申请号：US10368482
申请日：2003-02-20
申请人： Daisuke Takeuchi , Hideyuki Watanabe , Hideyo Okushi , Masataka Hasegawa , Masahiko Ogura , Naoto Kobayashi , Koji Kajimura , Sadanori Yamanaka
发明人： Daisuke Takeuchi , Hideyuki Watanabe , Hideyo Okushi , Masataka Hasegawa , Masahiko Ogura , Naoto Kobayashi , Koji Kajimura , Sadanori Yamanaka
IPC分类号： H01L214763
CPC分类号： H01L33/34 , H01L29/1602 , H01L29/6603 , H01L29/66136 , H01L29/861 , H01S5/3045 , H01S5/305
摘要： A diamond pn junction diode includes a p-type diamond thin-film layer formed on a substrate and an n-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the p-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer, or alternatively includes an n-type diamond thin-film layer formed on a substrate and a p-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the n-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer. A method of fabricating a diamond pn junction diode includes the steps of forming a p-type diamond thin-film layer on a substrate, forming a high-quality undoped diamond thin-film layer on the p-type diamond thin-film layer, and making the high-quality undoped diamond thin-film layer an n-type diamond thin-film layer by ion implantation of an impurity, or alternatively includes the steps of forming an n-type diamond thin-film layer on a substrate, forming a high-quality undoped diamond thin-film layer on the n-type diamond thin-film layer, and making the high-quality undoped diamond thin-film layer a p-type diamond thin-film layer by ion implantation of an impurity.
摘要翻译：金刚石pn结二极管包括形成在基板上的p型金刚石薄膜层和通过在p型金刚石薄膜层上形成高品质未掺杂的金刚石薄膜层形成的n型金刚石薄膜层，膜层，并将杂质离子注入到高质量未掺杂的金刚石薄膜层中，或者还可以包括形成在基板上的n型金刚石薄膜层和形成p型金刚石薄膜层的p型金刚石薄膜层，在n型金刚石薄膜层上的高品质未掺杂金刚石薄膜层，并将杂质离子注入到高品质未掺杂的金刚石薄膜层中。制造金刚石pn结二极管的方法包括以下步骤：在衬底上形成p型金刚石薄膜层，在p型金刚石薄膜层上形成高质量未掺杂的金刚石薄膜层;以及通过离子注入杂质使高品质未掺杂的金刚石薄膜层成为n型金刚石薄膜层，或者也可以包括在基板上形成n型金刚石薄膜层的步骤，形成高在n型金刚石薄膜层上的质量未掺杂的金刚石薄膜层，并且通过离子注入杂质使高品质未掺杂的金刚石薄膜层成为p型金刚石薄膜层。

3. 发明授权

US6132816A Method for producing homoepitaxial diamond thin films 失效
标题翻译：同质外延金刚石薄膜的制造方法
公开(公告)号：US6132816A
公开(公告)日：2000-10-17
申请号：US175959
申请日：1998-10-21
申请人： Daisuke Takeuchi , Hideyo Okushi , Koji Kajimura , Hideyuki Watanabe
发明人： Daisuke Takeuchi , Hideyo Okushi , Koji Kajimura , Hideyuki Watanabe
IPC分类号： C30B29/04 , C23C16/27 , C30B25/02 , C30B25/10 , H01L21/205 , H05H1/24 , C23C16/26
CPC分类号： C23C16/274 , C23C16/279 , C30B25/105
摘要： A method for producing homoepitaxial diamond thin film is provided which includes a step of effecting plasma assisted CVD with the carbon source concentration of a mixed gas of a carbon source and hydrogen set to a first low level for depositing a high-quality homoepitaxial diamond thin film on a substrate at a low film forming rate and a step of thereafter effecting the plasma assisted CVD with said carbon source concentration set to a second level higher than the first level.
摘要翻译：提供了一种制造同质外延金刚石薄膜的方法，该方法包括以碳源和氢气的混合气体的碳源浓度为第一低水平进行等离子体辅助CVD的步骤，用于沉积高品质同质外延金刚石薄膜在低成膜速度的基板上，然后进行等离子体辅助CVD的步骤，其中所述碳源浓度设定为高于第一水平的第二水平。

4. 发明授权

US06756086B2 Method for the fabrication of a diamond semiconductor 失效
标题翻译：金刚石半导体制造方法
公开(公告)号：US06756086B2
公开(公告)日：2004-06-29
申请号：US10090771
申请日：2002-03-06
申请人： Masataka Hasegawa , Masahiko Ogura , Daisuke Takeuchi , Hideyo Okushi , Naoto Kobayashi , Sadanori Yamanaka
发明人： Masataka Hasegawa , Masahiko Ogura , Daisuke Takeuchi , Hideyo Okushi , Naoto Kobayashi , Sadanori Yamanaka
IPC分类号： C23C1448
CPC分类号： H01L33/34 , C23C16/274 , H01L21/0415 , H01L21/265 , H01L29/1602 , Y10T428/30
摘要： A diamond semiconductor includes a high-quality thin diamond film layer with few crystal defects and few impurities, implanted with ions of dopant elements and controllable in conductivity determined by a kind and a concentration of the dopant elements. The diamond semiconductor is fabricated by a method including the step of implanting ions of dopant elements into a high-quality thin diamond film layer with few crystal defects and few impurities under conditions that can attain given distribution of concentrations of the dopant elements and with the high-quality thin diamond film layer kept to a temperature in accordance with the conditions so as not to be graphitized, to thereby enable the diamond semiconductor to have conductivity determined by a kind and a concentration of the dopant elements.
摘要翻译：金刚石半导体包括具有很少晶体缺陷和少量杂质的高品质薄金刚石膜层，注入掺杂元素的离子并且可通过掺杂元素的种类和浓度确定导电性。金刚石半导体是通过一种方法制造的，该方法包括以下步骤：将掺杂元素的离子注入到能够获得给定掺杂剂元素的浓度分布的条件下几乎没有晶体缺陷和少量杂质的高质量薄金刚石膜层质量的金刚石薄膜层根据条件保持温度以便不被石墨化，从而使金刚石半导体具有由掺杂剂元素的种类和浓度确定的导电性。

5. 发明申请

US20050093000A1 Silicon carbide semiconductor device and its manufacturing method 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US20050093000A1
公开(公告)日：2005-05-05
申请号：US11003599
申请日：2004-12-06
申请人： Satoshi Tanimoto , Hideyo Okushi
发明人： Satoshi Tanimoto , Hideyo Okushi
IPC分类号： H01L21/04 , H01L29/12 , H01L29/24 , H01L29/739 , H01L29/78 , H01L29/94 , H01L29/15 , H01L21/00
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/7395 , H01L29/7828 , H01L29/94
摘要： In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.
摘要翻译：在碳化硅半导体器件及其制造方法中，以与栅极电极不同且与单晶碳化硅基板接触的金属电极在预定的热处理下，在低于热氧化温度的温度下进行处理，形成栅极绝缘膜，并且足以在单晶碳化硅衬底和金属之间进行接触退火，整个栅极绝缘膜周围被单晶碳化硅衬底，场绝缘膜和栅极封闭电极。本发明可应用于MOS电容器，n沟道平面功率MOSFET和n沟道平面功率IGBT。

6. 发明申请

US20110037076A1 DIAMOND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：金刚石半导体器件及其制造方法
公开(公告)号：US20110037076A1
公开(公告)日：2011-02-17
申请号：US12988089
申请日：2009-03-06
申请人： Hiromitsu Kato , Toshiharu Makino , Masahiko Ogura , Hideyo Okushi , Satoshi Yamasaki
发明人： Hiromitsu Kato , Toshiharu Makino , Masahiko Ogura , Hideyo Okushi , Satoshi Yamasaki
IPC分类号： H01L29/16 , H01L21/02
CPC分类号： C30B29/04 , C30B25/02 , C30B25/105 , H01L21/02376 , H01L21/0243 , H01L21/02433 , H01L21/02527 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/041 , H01L21/042
摘要： The present invention is contemplated for providing a diamond semiconductor device where an impurity-doped diamond semiconductor is buried in a selected area, and a method of manufacturing the same.That is, a diamond semiconductor device having an impurity-doped diamond area selectively buried in a recessed portion formed in a diamond substrate; and a method of manufacturing a diamond semiconductor device, including the steps of selectively forming an recessed portion on the {100}-facet diamond semiconductor substrate, wherein the bottom face of the recessed portion is surrounded by the {100} facet and the side face of the recessed portion is surrounded by the {110} facet, and forming an impurity-doped diamond area by epitaxially growing diamond in the direction while doping with impurities and burying the recessed portion.
摘要翻译：本发明预期用于提供金刚石半导体器件，其中杂质掺杂的金刚石半导体被埋在所选择的区域中，及其制造方法。也就是说，具有掺杂金刚石区域的金刚石半导体器件选择性地埋在形成在金刚石衬底中的凹陷部分中; 以及制造金刚石半导体器件的方法，包括以下步骤：在{100}面金刚石半导体衬底上选择性地形成凹陷部分，其中凹陷部分的底面由{100}面和侧面凹陷部分被{110}面围绕，并且通过在<111>方向外延生长金刚石并掺杂杂质并埋入凹陷部分而形成杂质掺杂金刚石区域。

7. 发明授权

US06833562B2 Silicon carbide semiconductor device and its manufacturing method 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US06833562B2
公开(公告)日：2004-12-21
申请号：US10307363
申请日：2002-12-02
申请人： Satoshi Tanimoto , Hideyo Okushi
发明人： Satoshi Tanimoto , Hideyo Okushi
IPC分类号： H01L310312
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/7395 , H01L29/7828 , H01L29/94
摘要： In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.
摘要翻译：在碳化硅半导体器件及其制造方法中，以与栅极电极不同且与单晶碳化硅基板接触的金属电极在预定的热处理下，在低于热氧化温度的温度下进行处理，形成栅极绝缘膜，并且足以在单晶碳化硅衬底和金属之间进行接触退火，整个栅极绝缘膜周围被单晶碳化硅衬底，场绝缘膜和栅极封闭电极。本发明可应用于MOS电容器，n沟道平面功率MOSFET和n沟道平面功率IGBT。

8. 发明申请

US20110017991A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110017991A1
公开(公告)日：2011-01-27
申请号：US12934199
申请日：2009-02-27
申请人： Satoshi Tanimoto , Norihiko Kiritani , Toshiharu Makino , Masahiko Ogura , Norio Tokuda , Hiromitsu Kato , Hideyo Okushi , Satoshi Yamasaki
发明人： Satoshi Tanimoto , Norihiko Kiritani , Toshiharu Makino , Masahiko Ogura , Norio Tokuda , Hiromitsu Kato , Hideyo Okushi , Satoshi Yamasaki
IPC分类号： H01L29/12 , H01L29/06 , H01L29/22 , H01L29/16 , H01L29/24 , H01L29/20
CPC分类号： H01L29/861 , H01L29/1602 , H01L29/1608 , H01L29/20 , H01L29/2003 , H01L29/22 , H01L29/45 , H01L29/452 , H01L29/456 , H01L29/47 , H01L29/475 , H01L29/872
摘要： In this junction element 1, when a forward voltage is applied, a depletion layer is formed in a semiconductor layer 2, prohibiting electrons present in an electrode layer 4 to move into the semiconductor layer 2. For this reason, a majority of holes in a semiconductor layer 3 do not disappear by recombination with conduction electrons in the semiconductor layer 2, but reach the electrode layer 4 while diffusing into the semiconductor layer 2. Accordingly, the junction element 1 can serve as a good conductor for holes, while avoiding the influence of a resistance value, and allows a current to flow therethrough at a level equal to or more than that achieved by a semiconductor element formed of a Si or SiC semiconductor. The present invention is applicable to any semiconductor material in which at least one of a donor level and an acceptor level is located at a sufficiently deep position beyond a thermal excitation energy at an operating temperature, such as diamond, zinc oxide (ZnO), aluminum nitride (AlN), or boron nitride (BN). The present invention is also applicable to even a material having a shallow impurity level at room temperature, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or germanium (Ge), as long as operation is performed at such a low temperature that the thermal excitation energy can be sufficiently small.
摘要翻译：在该接合元件1中，当施加正向电压时，在半导体层2中形成耗尽层，禁止存在于电极层4中的电子移动到半导体层2中。因此，大部分孔半导体层3不会通过与半导体层2中的导电电子的复合而消失，而是在扩散到半导体层2中的同时到达电极层4.因此，接合元件1可以用作孔的良导体，同时避免影响的电阻值，并且允许电流以等于或大于由Si或SiC半导体形成的半导体元件实现的电平流过。本发明可应用于任何半导体材料，其中施主电平和受主电平中的至少一个位于超过工作温度下的热激发能的足够深的位置，例如金刚石，氧化锌（ZnO），铝氮化物（AlN）或氮化硼（BN）。本发明甚至也可应用于诸如硅（Si），碳化硅（SiC），氮化镓（GaN），砷化镓（GaAs）或锗（Ge）等室温下具有浅杂质水平的材料，只要在如此低的温度下进行操作即可使热激发能足够小。

9. 发明授权

US07535025B2 Structure and manufacturing method for a silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的结构和制造方法
公开(公告)号：US07535025B2
公开(公告)日：2009-05-19
申请号：US11003599
申请日：2004-12-06
申请人： Satoshi Tanimoto , Hideyo Okushi
发明人： Satoshi Tanimoto , Hideyo Okushi
IPC分类号： H01L29/24
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/7395 , H01L29/7828 , H01L29/94
摘要： In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.
摘要翻译：在碳化硅半导体器件及其制造方法中，以与栅极电极不同且与单晶碳化硅基板接触的金属电极在预定的热处理下，在低于热氧化温度的温度下进行处理，形成栅极绝缘膜，并且足以在单晶碳化硅衬底和金属之间进行接触退火，整个栅极绝缘膜周围被单晶碳化硅衬底，场绝缘膜和栅极封闭电极。本发明可应用于MOS电容器，n沟道平面功率MOSFET和n沟道平面功率IGBT。

10. 发明授权

US09136400B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09136400B2
公开(公告)日：2015-09-15
申请号：US12934199
申请日：2009-02-27
申请人： Satoshi Tanimoto , Norihiko Kiritani , Toshiharu Makino , Masahiko Ogura , Norio Tokuda , Hiromitsu Kato , Hideyo Okushi , Satoshi Yamasaki
发明人： Satoshi Tanimoto , Norihiko Kiritani , Toshiharu Makino , Masahiko Ogura , Norio Tokuda , Hiromitsu Kato , Hideyo Okushi , Satoshi Yamasaki
IPC分类号： H01L21/00 , H01L29/861 , H01L29/16 , H01L29/20 , H01L29/22 , H01L29/45 , H01L29/47 , H01L29/872
CPC分类号： H01L29/861 , H01L29/1602 , H01L29/1608 , H01L29/20 , H01L29/2003 , H01L29/22 , H01L29/45 , H01L29/452 , H01L29/456 , H01L29/47 , H01L29/475 , H01L29/872
摘要： In this junction element 1, when a forward voltage is applied, a depletion layer is formed in a semiconductor layer 2, prohibiting electrons present in an electrode layer 4 to move into the semiconductor layer 2. For this reason, a majority of holes in a semiconductor layer 3 do not disappear by recombination with conduction electrons in the semiconductor layer 2, but reach the electrode layer 4 while diffusing into the semiconductor layer 2. Accordingly, the junction element 1 can serve as a good conductor for holes, while avoiding the influence of a resistance value, and allows a current to flow therethrough at a level equal to or more than that achieved by a semiconductor element formed of a Si or SiC semiconductor. The present invention is applicable to any semiconductor material in which at least one of a donor level and an acceptor level is located at a sufficiently deep position beyond a thermal excitation energy at an operating temperature, such as diamond, zinc oxide (ZnO), aluminum nitride (AlN), or boron nitride (BN). The present invention is also applicable to even a material having a shallow impurity level at room temperature, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or germanium (Ge), as long as operation is performed at such a low temperature that the thermal excitation energy can be sufficiently small.
摘要翻译：在该接合元件1中，当施加正向电压时，在半导体层2中形成耗尽层，禁止存在于电极层4中的电子移动到半导体层2中。因此，大部分孔半导体层3不会通过与半导体层2中的导电电子的复合而消失，而是在扩散到半导体层2中的同时到达电极层4.因此，接合元件1可以用作孔的良导体，同时避免影响的电阻值，并且允许电流以等于或大于由Si或SiC半导体形成的半导体元件实现的电平流过。本发明可应用于任何半导体材料，其中施主电平和受主电平中的至少一个位于超过工作温度下的热激发能的足够深的位置，例如金刚石，氧化锌（ZnO），铝氮化物（AlN）或氮化硼（BN）。本发明甚至也可应用于诸如硅（Si），碳化硅（SiC），氮化镓（GaN），砷化镓（GaAs）或锗（Ge）等室温下具有浅杂质水平的材料，只要在如此低的温度下进行操作即可使热激发能足够小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式