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    • 2. 发明授权
    • Shape measurement method and shape measurement apparatus for tires
    • 轮胎的形状测量方法和形状测量装置
    • US09175952B2
    • 2015-11-03
    • US13635611
    • 2011-03-18
    • Akinobu MizutaniDaisuke KatoAkira TogiiKenichi Okude
    • Akinobu MizutaniDaisuke KatoAkira TogiiKenichi Okude
    • G01M17/02G01B11/16G01B11/22G01B11/24
    • G01B11/24G01B11/06G01B2210/52G01M17/027
    • A shape measurement method for a tire includes: detecting an outer surface shape data and an inner surface shape of the tire from image data of the outer surface and the inner surface; subjecting irregularities along the tire circumferential direction around the tire in the outer surface shape data and in the inner surface shape data to Fourier transformation to take out primary waveform components respectively; adjusting the tire circumferential positions of both of the waveform components to adjust the tire circumferential positions thereof; adjusting the tire radial direction cross section positions of the outer surface shape data and the inner surface shape data from information about the placement angles and the positions of the first camera and the second camera; and synthesizing the outer surface shape data and the inner surface shape data based on the adjusted tire circumferential positions and the tire radial direction cross section positions.
    • 轮胎的形状测量方法包括:根据外表面和内表面的图像数据检测轮胎的外表面形状数据和内表面形状; 在外表面形状数据和内表面形状数据中沿着轮胎周向轮胎周围的不规则性分别进行傅立叶变换以分别取出主波形成分; 调整两个波形分量的轮胎周向位置,以调整其轮胎周向位置; 从关于第一相机和第二相机的位置角度和位置的信息调整外表面形状数据和内表面形状数据的轮胎径向横截面位置; 以及基于所调整的轮胎周向位置和轮胎径向横截面位置来合成外表面形状数据和内表面形状数据。
    • 9. 发明授权
    • Semiconductor integrated circuit device having fuses and fuse latch circuits
    • 具有保险丝和熔丝锁存电路的半导体集成电路器件
    • US06272061B1
    • 2001-08-07
    • US09652158
    • 2000-08-31
    • Daisuke KatoYohji Watanabe
    • Daisuke KatoYohji Watanabe
    • G11C700
    • G11C5/025G11C29/80
    • A semiconductor integrated circuit device has a semiconductor integrated circuit with first layout sections where fuses are laid out and second layout sections where fuse latch circuits, which correspond to the fuses, are laid out. The first layout sections are disposed in a first repetition pitch in a fuse area, while the second layout sections are laid out at a second repetition pitch smaller than the first repetition pitch in a fuse latch circuit area. A third layout section is laid out in a space caused by the difference between the first and second repetition pitches. In the third layout section, at least one of patterns which are unrepeatable in each of the second layout sections and the patterns which do not need to be repeated in each of the second layout sections.
    • 半导体集成电路器件具有半导体集成电路,其具有布置熔丝的第一布局部分,布置与保险丝对应的熔丝锁存电路的第二布局部分。 第一布局部分以熔丝区域中的第一重复间距布置,而第二布局部分以比熔丝锁存电路区域中的第一重复间距小的第二重复间距布置。 在由第一和第二重复间距之间的差异引起的空间中布置第三布局部分。 在第三布置部分中,在每个第二布局部分中的每一个中不可重复的图案中的至少一个和不需要在每个第二布局部分中重复的图案。