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1. 发明申请

US20130002856A1 SHAPE MEASUREMENT METHOD AND SHAPE MEASUREMENT APPARATUS FOR TIRES 有权
标题翻译：形状测量方法和轮胎测量设备
公开(公告)号：US20130002856A1
公开(公告)日：2013-01-03
申请号：US13635611
申请日：2011-03-18
申请人： Akinobu Mizutani , Daisuke Kato , Akira Togii , Kenichi Okude
发明人： Akinobu Mizutani , Daisuke Kato , Akira Togii , Kenichi Okude
IPC分类号： H04N7/18
CPC分类号： G01B11/24 , G01B11/06 , G01B2210/52 , G01M17/027
摘要： A shape measurement method for a tire includes: detecting an outer surface shape data and an inner surface shape of the tire from image data of the outer surface and the inner surface; subjecting irregularities along the tire circumferential direction around the tire in the outer surface shape data and in the inner surface shape data to Fourier transformation to take out primary waveform components respectively; adjusting the tire circumferential positions of both of the waveform components to adjust the tire circumferential positions thereof; adjusting the tire radial direction cross section positions of the outer surface shape data and the inner surface shape data from information about the placement angles and the positions of the first camera and the second camera; and synthesizing the outer surface shape data and the inner surface shape data based on the adjusted tire circumferential positions and the tire radial direction cross section positions.
摘要翻译：轮胎的形状测量方法包括：根据外表面和内表面的图像数据检测轮胎的外表面形状数据和内表面形状; 在外表面形状数据和内表面形状数据中沿着轮胎周向轮胎周围的不规则性分别进行傅立叶变换以分别取出主波形成分; 调整两个波形分量的轮胎周向位置，以调整其轮胎周向位置; 从关于第一相机和第二相机的位置角度和位置的信息调整外表面形状数据和内表面形状数据的轮胎径向横截面位置; 以及基于所调整的轮胎周向位置和轮胎径向横截面位置来合成外表面形状数据和内表面形状数据。

2. 发明授权

US09175952B2 Shape measurement method and shape measurement apparatus for tires 有权
标题翻译：轮胎的形状测量方法和形状测量装置
公开(公告)号：US09175952B2
公开(公告)日：2015-11-03
申请号：US13635611
申请日：2011-03-18
申请人： Akinobu Mizutani , Daisuke Kato , Akira Togii , Kenichi Okude
发明人： Akinobu Mizutani , Daisuke Kato , Akira Togii , Kenichi Okude
IPC分类号： G01M17/02 , G01B11/16 , G01B11/22 , G01B11/24
CPC分类号： G01B11/24 , G01B11/06 , G01B2210/52 , G01M17/027
摘要： A shape measurement method for a tire includes: detecting an outer surface shape data and an inner surface shape of the tire from image data of the outer surface and the inner surface; subjecting irregularities along the tire circumferential direction around the tire in the outer surface shape data and in the inner surface shape data to Fourier transformation to take out primary waveform components respectively; adjusting the tire circumferential positions of both of the waveform components to adjust the tire circumferential positions thereof; adjusting the tire radial direction cross section positions of the outer surface shape data and the inner surface shape data from information about the placement angles and the positions of the first camera and the second camera; and synthesizing the outer surface shape data and the inner surface shape data based on the adjusted tire circumferential positions and the tire radial direction cross section positions.
摘要翻译：轮胎的形状测量方法包括：根据外表面和内表面的图像数据检测轮胎的外表面形状数据和内表面形状; 在外表面形状数据和内表面形状数据中沿着轮胎周向轮胎周围的不规则性分别进行傅立叶变换以分别取出主波形成分; 调整两个波形分量的轮胎周向位置，以调整其轮胎周向位置; 从关于第一相机和第二相机的位置角度和位置的信息调整外表面形状数据和内表面形状数据的轮胎径向横截面位置; 以及基于所调整的轮胎周向位置和轮胎径向横截面位置来合成外表面形状数据和内表面形状数据。

3. 发明申请

US20060256625A1 Semiconductor memory device 失效
公开(公告)号：US20060256625A1
公开(公告)日：2006-11-16
申请号：US11490234
申请日：2006-07-21
申请人： Yasuyuki Kajitani , Daisuke Kato
发明人： Yasuyuki Kajitani , Daisuke Kato
IPC分类号： G11C7/10
CPC分类号： G11C29/50008 , G11C7/08 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/065 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/10897
摘要： A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.

4. 发明授权

US07079432B2 Semiconductor storage device formed to optimize test technique and redundancy technology 失效
标题翻译：形成半导体存储设备，以优化测试技术和冗余技术
公开(公告)号：US07079432B2
公开(公告)日：2006-07-18
申请号：US11040851
申请日：2005-01-20
申请人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
发明人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C29/26 , G11C29/787 , G11C2029/2602
摘要： A semiconductor storage device has a function of simultaneously activating a plurality of word lines connected to the same bit line via cell transistors. The semiconductor storage device comprises a column redundancy system that sets repair regions of column redundancy based on row addresses. By the column redundancy system, the repair regions are set to cause the plurality of word lines which can be activated together to belong to the same repair region, when the repair regions are set to divide the bit line.
摘要翻译：半导体存储装置具有通过单元晶体管同时激活连接到同一位线的多个字线的功能。半导体存储装置包括基于行地址设置列冗余的修复区域的列冗余系统。通过列冗余系统，当修复区域被设置为分割位线时，修复区域被设置为使得可以一起被激活的多个字线属于同一修复区域。

5. 发明申请

US20050226081A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050226081A1
公开(公告)日：2005-10-13
申请号：US11095883
申请日：2005-04-01
申请人： Yasuyuki Kajitani , Daisuke Kato
发明人： Yasuyuki Kajitani , Daisuke Kato
IPC分类号： H01L27/10 , G11C7/12 , G11C8/00 , G11C11/401 , G11C11/409 , G11C11/4094 , H01L21/8242 , H01L27/108
CPC分类号： G11C29/50008 , G11C7/08 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/065 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/10897
摘要： A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.
摘要翻译：一种半导体存储器件包括具有多个存储单元的存储单元阵列，在存储单元之间传送数据的多个第一位线对，对应于多个第一位线对设置的多个第二位线对，设置成将多个第一位线对连接到多个第二位线对的多个可变电阻元件，对应于多个第二位线对设置的多个数据线对，多个输入/输出门，在所述多个第二位线对和所述多个数据线对之间传送数据，放大传送到所述多个第二位线对的数据的多个读出放大器电路以及控制所述多个第二位线对的电阻值的位线隔离控制电路多个可变电阻元件。

6. 发明授权

US06496435B2 Sense amplifier control circuit of semiconductor memory device 有权
标题翻译：半导体存储器件的感应放大器控制电路
公开(公告)号：US06496435B2
公开(公告)日：2002-12-17
申请号：US10035043
申请日：2001-12-27
申请人： Daisuke Kato
发明人： Daisuke Kato
IPC分类号： G11C702
CPC分类号： G11C7/065 , G11C11/4091 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier control circuit for use in a semiconductor memory device is provided which comprises a sense amplifier comprising first transistors of a first conductivity type connected in the form of a latch type differential amplifier, a set driver corresponding to the sense amplifier and the set driver comprising a second transistor of a second conductivity type for connecting the common source line of the latch type differential amplifier to a restore power supply line.
摘要翻译：提供了一种用于半导体存储器件的读出放大器控制电路，其包括一个读出放大器，该读出放大器包括以锁存型差分放大器形式连接的第一导电类型的第一晶体管，与读出放大器对应的设定驱动器和设定驱动器包括用于将锁存型差分放大器的公共源极线连接到恢复电源线的第二导电类型的第二晶体管。

7. 发明授权

US06373772B1 Semiconductor integrated circuit device having fuses and fuse latch circuits 有权
公开(公告)号：US06373772B1
公开(公告)日：2002-04-16
申请号：US09886490
申请日：2001-06-22
申请人： Daisuke Kato , Yohji Watanabe
发明人： Daisuke Kato , Yohji Watanabe
IPC分类号： G11C700
摘要： A semiconductor integrated circuit device has a semiconductor integrated circuit with first layout sections where fuses are laid out and second layout sections where fuse latch circuits, which correspond to the fuses, are laid out. The first layout sections are disposed in a first repetition pitch in a fuse area, while the second layout sections are laid out at a second repetition pitch smaller than the first repetition pitch in a fuse latch circuit area. A third layout section is laid out in a space caused by the difference between the first and second repetition pitches. In the third layout section, at least one of patterns which are unrepeatable in each of the second layout sections and the patterns which do not need to be repeated in each of the second layout sections.

8. 发明授权

US06343038B1 Semiconductor memory device of shared sense amplifier system 有权
标题翻译：共享读出放大器系统的半导体存储器件
公开(公告)号：US06343038B1
公开(公告)日：2002-01-29
申请号：US09653264
申请日：2000-08-31
申请人： Eiichi Makino , Yohji Watanabe , Daisuke Kato
发明人： Eiichi Makino , Yohji Watanabe , Daisuke Kato
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/4094 , G11C29/14
摘要： In a semiconductor memory device including a bit line precharge/equalizing circuit, the control system of the bit line precharge/equalizing circuit is changed in the normal operation mode and in the test mode. In the test mode, the bit line precharge/equalizing circuit is temporarily turned ON when an internal activation signal becomes non-active and then the bit line precharge/equalizing circuit is turned OFF after the potentials of paired bit lines are completely equalized.
摘要翻译：在包括位线预充电/均衡电路的半导体存储器件中，位线预充电/均衡电路的控制系统在正常工作模式和测试模式下改变。在测试模式下，当内部激活信号变为非有效时，位线预充电/均衡电路暂时导通，然后位线预充电/均衡电路在配对位线的电位完全相等之后变为截止。

9. 发明授权

US06272061B1 Semiconductor integrated circuit device having fuses and fuse latch circuits 失效
标题翻译：具有保险丝和熔丝锁存电路的半导体集成电路器件
公开(公告)号：US06272061B1
公开(公告)日：2001-08-07
申请号：US09652158
申请日：2000-08-31
申请人： Daisuke Kato , Yohji Watanabe
发明人： Daisuke Kato , Yohji Watanabe
IPC分类号： G11C700
CPC分类号： G11C5/025 , G11C29/80
摘要： A semiconductor integrated circuit device has a semiconductor integrated circuit with first layout sections where fuses are laid out and second layout sections where fuse latch circuits, which correspond to the fuses, are laid out. The first layout sections are disposed in a first repetition pitch in a fuse area, while the second layout sections are laid out at a second repetition pitch smaller than the first repetition pitch in a fuse latch circuit area. A third layout section is laid out in a space caused by the difference between the first and second repetition pitches. In the third layout section, at least one of patterns which are unrepeatable in each of the second layout sections and the patterns which do not need to be repeated in each of the second layout sections.
摘要翻译：半导体集成电路器件具有半导体集成电路，其具有布置熔丝的第一布局部分，布置与保险丝对应的熔丝锁存电路的第二布局部分。第一布局部分以熔丝区域中的第一重复间距布置，而第二布局部分以比熔丝锁存电路区域中的第一重复间距小的第二重复间距布置。在由第一和第二重复间距之间的差异引起的空间中布置第三布局部分。在第三布置部分中，在每个第二布局部分中的每一个中不可重复的图案中的至少一个和不需要在每个第二布局部分中重复的图案。

10. 发明授权

US5969998A MOS semiconductor device with memory cells each having storage capacitor and transfer transistor 有权
公开(公告)号：US5969998A
公开(公告)日：1999-10-19
申请号：US213773
申请日：1998-12-17
申请人： Yukihito Oowaki , Daisuke Kato , Daisaburo Takashima
发明人： Yukihito Oowaki , Daisuke Kato , Daisaburo Takashima
IPC分类号： G11C11/407 , G11C7/06 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4096 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00 , G11C11/24
CPC分类号： G11C11/4096 , G11C11/4091 , G11C7/065
摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

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