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1. 发明授权

US07414907B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07414907B2
公开(公告)日：2008-08-19
申请号：US11766486
申请日：2007-06-21
申请人： Yasuyuki Kajitani , Daisuke Kato
发明人： Yasuyuki Kajitani , Daisuke Kato
IPC分类号： G11C7/02
CPC分类号： G11C29/50008 , G11C7/08 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/065 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/10897
摘要： A semiconductor memory device including a memory cell array which has a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs which transfer data among the memory cells, a sense amplifier bank which includes a plurality of sense amplifiers, the plurality of sense amplifiers including a plurality of sense amplifier circuits, and the plurality of sense amplifier circuits being connected respectively to the plurality of bit line pairs to amplify data transferred to the bit line pairs, a plurality of word lines connected to the memory cells, a plurality of wirings disposed respectively corresponding to the plurality of word lines and above the plurality of word lines, and a plurality of stitch portions which connect the plurality of word lines to the plurality of wirings every predetermined intervals. Two active areas in which the sense amplifier circuit is formed respectively in both sides of a stitch area corresponding to each of the stitch portions in the sense amplifier bank are connected to each other, and a dummy transistor is disposed on the connected active areas.
摘要翻译：一种半导体存储器件，包括具有以矩阵形式布置的多个存储单元的存储单元阵列，在存储单元之间传送数据的多个位线对，包括多个读出放大器的读出放大器组，包括多个读出放大器电路的读出放大器，并且多个读出放大器电路分别连接到多个位线对，以放大传送到位线对的数据，连接到存储器单元的多条字线，分别对应于多个字线并且在多个字线上方布置的多个布线，以及多个针对每隔预定间隔将多条字线连接到多条布线的线迹部分。在与感测放大器组中的每个针脚部分相对应的针脚区域的两侧分别形成读出放大器电路的两个有源区域彼此连接，并且在连接的有源区域上设置虚设晶体管。

2. 发明申请

US20060171226A1 Semiconductor memory device with column to be selected by bit line selection signal 审中-公开
标题翻译：具有列的半导体存储器件由位线选择信号选择
公开(公告)号：US20060171226A1
公开(公告)日：2006-08-03
申请号：US11240507
申请日：2005-10-03
申请人： Yasuyuki Kajitani , Daisuke Kato , Mariko Kaku
发明人： Yasuyuki Kajitani , Daisuke Kato , Mariko Kaku
IPC分类号： G11C7/02
CPC分类号： G11C11/4087 , G11C7/08 , G11C11/4091 , G11C29/808 , G11C2207/002
摘要： A sense amplifier bank contains sense amplifier circuits, data line pairs and selection circuits. The selection circuits set one of a connection status and a disconnection status between a bit line pair and the data line pair in accordance with a bit line selection signal. A control circuit controls the bit line selection signal supplied to the selection circuits. A global bit line selection signal line is connected to the control circuit, and receives the bit line section signal therefrom. Drive circuits, input portions of which are connected to the global bit line selection signal line, drive the bit line selection signal supplied to the global bit line selection signal line and output it, and the drive circuits are arranged within the sense amplifier bank. A local bit line selection signal line supplies the bit line selection signal driven by the drive circuit to the selection circuit.
摘要翻译：读出放大器组包含读出放大器电路，数据线对和选择电路。选择电路根据位线选择信号设置位线对和数据线对之间的连接状态和断开状态之一。控制电路控制提供给选择电路的位线选择信号。全局位线选择信号线连接到控制电路，并从其接收位线部分信号。驱动电路，其输入部分连接到全局位线选择信号线，驱动提供给全局位线选择信号线的位线选择信号并将其输出，驱动电路被布置在读出放大器组内。局部位线选择信号线将由驱动电路驱动的位线选择信号提供给选择电路。

3. 发明申请

US20080031065A1 SEMICONDUCTOR MEMORY DEVICE WITH COLUMN TO BE SELECTED BY BIT LINE SELECTION SIGNAL 审中-公开
标题翻译：具有通过位线选择信号选择的列的半导体存储器件
公开(公告)号：US20080031065A1
公开(公告)日：2008-02-07
申请号：US11865398
申请日：2007-10-01
申请人： Yasuyuki KAJITANI , Daisuke Kato , Mariko Kaku
发明人： Yasuyuki KAJITANI , Daisuke Kato , Mariko Kaku
IPC分类号： G11C7/02
CPC分类号： G11C11/4087 , G11C7/08 , G11C11/4091 , G11C29/808 , G11C2207/002
摘要： A sense amplifier bank contains sense amplifier circuits, data line pairs and selection circuits. The selection circuits set one of a connection status and a disconnection status between a bit line pair and the data line pair in accordance with a bit line selection signal. A control circuit controls the bit line selection signal supplied to the selection circuits. A global bit line selection signal line is connected to the control circuit, and receives the bit line section signal therefrom. Drive circuits, input portions of which are connected to the global bit line selection signal line, drive the bit line selection signal supplied to the global bit line selection signal line and output it, and the drive circuits are arranged within the sense amplifier bank. A local bit line selection signal line supplies the bit line selection signal driven by the drive circuit to the selection circuit.
摘要翻译：读出放大器组包含读出放大器电路，数据线对和选择电路。选择电路根据位线选择信号设置位线对和数据线对之间的连接状态和断开状态之一。控制电路控制提供给选择电路的位线选择信号。全局位线选择信号线连接到控制电路，并从其接收位线部分信号。驱动电路，其输入部分连接到全局位线选择信号线，驱动提供给全局位线选择信号线的位线选择信号并将其输出，驱动电路被布置在读出放大器组内。局部位线选择信号线将由驱动电路驱动的位线选择信号提供给选择电路。

4. 发明授权

US07251176B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07251176B2
公开(公告)日：2007-07-31
申请号：US11490234
申请日：2006-07-21
申请人： Yasuyuki Kajitani , Daisuke Kato
发明人： Yasuyuki Kajitani , Daisuke Kato
IPC分类号： G11C7/02
CPC分类号： G11C29/50008 , G11C7/08 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/065 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/10897
摘要： A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.
摘要翻译：一种半导体存储器件包括具有多个存储单元的存储单元阵列，在存储单元之间传送数据的多个第一位线对，对应于多个第一位线对设置的多个第二位线对，设置成将多个第一位线对连接到多个第二位线对的多个可变电阻元件，对应于多个第二位线对设置的多个数据线对，多个输入/输出门，在所述多个第二位线对和所述多个数据线对之间传送数据，放大传送到所述多个第二位线对的数据的多个读出放大器电路以及控制所述多个第二位线对的电阻值的位线隔离控制电路多个可变电阻元件。

5. 发明申请

US20070258303A1 Semiconductor Memory Device 失效
标题翻译：半导体存储器件
公开(公告)号：US20070258303A1
公开(公告)日：2007-11-08
申请号：US11766486
申请日：2007-06-21
申请人： Yasuyuki Kajitani , Daisuke Kato
发明人： Yasuyuki Kajitani , Daisuke Kato
IPC分类号： G11C7/02
CPC分类号： G11C29/50008 , G11C7/08 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/065 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/10897
摘要： A semiconductor memory device including a memory cell array which has a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs which transfer data among the memory cells, a sense amplifier bank which includes a plurality of sense amplifiers, the plurality of sense amplifiers including a plurality of sense amplifier circuits, and the plurality of sense amplifier circuits being connected respectively to the plurality of bit line pairs to amplify data transferred to the bit line pairs, a plurality of word lines connected to the memory cells, a plurality of wirings disposed respectively corresponding to the plurality of word lines and above the plurality of word lines, and a plurality of stitch portions which connect the plurality of word lines to the plurality of wirings every predetermined intervals. Two active areas in which the sense amplifier circuit is formed respectively in both sides of a stitch area corresponding to each of the stitch portions in the sense amplifier bank are connected to each other, and a dummy transistor is disposed on the connected active areas.
摘要翻译：一种半导体存储器件，包括具有以矩阵形式布置的多个存储单元的存储单元阵列，在存储单元之间传送数据的多个位线对，包括多个读出放大器的读出放大器组，包括多个读出放大器电路的读出放大器，并且多个读出放大器电路分别连接到多个位线对，以放大传送到位线对的数据，连接到存储器单元的多条字线，分别对应于多个字线并且在多个字线上方布置的多个布线，以及多个针对每隔预定间隔将多条字线连接到多条布线的线迹部分。在与感测放大器组中的每个针脚部分相对应的针脚区域的两侧分别形成读出放大器电路的两个有源区域彼此连接，并且在连接的有源区域上设置虚设晶体管。

6. 发明授权

US07102947B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07102947B2
公开(公告)日：2006-09-05
申请号：US11095883
申请日：2005-04-01
申请人： Yasuyuki Kajitani , Daisuke Kato
发明人： Yasuyuki Kajitani , Daisuke Kato
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C29/50008 , G11C7/08 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/065 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/10897
摘要： A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.
摘要翻译：一种半导体存储器件包括具有多个存储单元的存储单元阵列，在存储单元之间传送数据的多个第一位线对，对应于多个第一位线对设置的多个第二位线对，设置成将多个第一位线对连接到多个第二位线对的多个可变电阻元件，对应于多个第二位线对设置的多个数据线对，多个输入/输出门，在所述多个第二位线对和所述多个数据线对之间传送数据，放大传送到所述多个第二位线对的数据的多个读出放大器电路以及控制所述多个第二位线对的电阻值的位线隔离控制电路多个可变电阻元件。

7. 发明申请

US20060256625A1 Semiconductor memory device 失效
公开(公告)号：US20060256625A1
公开(公告)日：2006-11-16
申请号：US11490234
申请日：2006-07-21
申请人： Yasuyuki Kajitani , Daisuke Kato
发明人： Yasuyuki Kajitani , Daisuke Kato
IPC分类号： G11C7/10
CPC分类号： G11C29/50008 , G11C7/08 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/065 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/10897
摘要： A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.

8. 发明申请

US20050226081A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050226081A1
公开(公告)日：2005-10-13
申请号：US11095883
申请日：2005-04-01
申请人： Yasuyuki Kajitani , Daisuke Kato
发明人： Yasuyuki Kajitani , Daisuke Kato
IPC分类号： H01L27/10 , G11C7/12 , G11C8/00 , G11C11/401 , G11C11/409 , G11C11/4094 , H01L21/8242 , H01L27/108
CPC分类号： G11C29/50008 , G11C7/08 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/065 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/10897
摘要： A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bit line pairs, a plurality of variable resistance elements disposed to connect the plurality of first bit line pairs to the plurality of second bit line pairs, a plurality of data line pairs disposed corresponding to the plurality of second bit line pairs, a plurality of input/output gates which transfer data between the plurality of second bit line pairs and the plurality of data line pairs, a plurality of sense amplifier circuits which amplify data transferred to the plurality of second bit line pairs, and a bit line isolation control circuit which controls resistance values of the plurality of variable resistance elements.
摘要翻译：一种半导体存储器件包括具有多个存储单元的存储单元阵列，在存储单元之间传送数据的多个第一位线对，对应于多个第一位线对设置的多个第二位线对，设置成将多个第一位线对连接到多个第二位线对的多个可变电阻元件，对应于多个第二位线对设置的多个数据线对，多个输入/输出门，在所述多个第二位线对和所述多个数据线对之间传送数据，放大传送到所述多个第二位线对的数据的多个读出放大器电路以及控制所述多个第二位线对的电阻值的位线隔离控制电路多个可变电阻元件。

9. 发明授权

US09175952B2 Shape measurement method and shape measurement apparatus for tires 有权
标题翻译：轮胎的形状测量方法和形状测量装置
公开(公告)号：US09175952B2
公开(公告)日：2015-11-03
申请号：US13635611
申请日：2011-03-18
申请人： Akinobu Mizutani , Daisuke Kato , Akira Togii , Kenichi Okude
发明人： Akinobu Mizutani , Daisuke Kato , Akira Togii , Kenichi Okude
IPC分类号： G01M17/02 , G01B11/16 , G01B11/22 , G01B11/24
CPC分类号： G01B11/24 , G01B11/06 , G01B2210/52 , G01M17/027
摘要： A shape measurement method for a tire includes: detecting an outer surface shape data and an inner surface shape of the tire from image data of the outer surface and the inner surface; subjecting irregularities along the tire circumferential direction around the tire in the outer surface shape data and in the inner surface shape data to Fourier transformation to take out primary waveform components respectively; adjusting the tire circumferential positions of both of the waveform components to adjust the tire circumferential positions thereof; adjusting the tire radial direction cross section positions of the outer surface shape data and the inner surface shape data from information about the placement angles and the positions of the first camera and the second camera; and synthesizing the outer surface shape data and the inner surface shape data based on the adjusted tire circumferential positions and the tire radial direction cross section positions.
摘要翻译：轮胎的形状测量方法包括：根据外表面和内表面的图像数据检测轮胎的外表面形状数据和内表面形状; 在外表面形状数据和内表面形状数据中沿着轮胎周向轮胎周围的不规则性分别进行傅立叶变换以分别取出主波形成分; 调整两个波形分量的轮胎周向位置，以调整其轮胎周向位置; 从关于第一相机和第二相机的位置角度和位置的信息调整外表面形状数据和内表面形状数据的轮胎径向横截面位置; 以及基于所调整的轮胎周向位置和轮胎径向横截面位置来合成外表面形状数据和内表面形状数据。

10. 发明授权

US07079432B2 Semiconductor storage device formed to optimize test technique and redundancy technology 失效
标题翻译：形成半导体存储设备，以优化测试技术和冗余技术
公开(公告)号：US07079432B2
公开(公告)日：2006-07-18
申请号：US11040851
申请日：2005-01-20
申请人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
发明人： Daisuke Kato , Takashi Taira , Kenji Ishizuka , Yohji Watanabe , Munehiro Yoshida
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C29/26 , G11C29/787 , G11C2029/2602
摘要： A semiconductor storage device has a function of simultaneously activating a plurality of word lines connected to the same bit line via cell transistors. The semiconductor storage device comprises a column redundancy system that sets repair regions of column redundancy based on row addresses. By the column redundancy system, the repair regions are set to cause the plurality of word lines which can be activated together to belong to the same repair region, when the repair regions are set to divide the bit line.
摘要翻译：半导体存储装置具有通过单元晶体管同时激活连接到同一位线的多个字线的功能。半导体存储装置包括基于行地址设置列冗余的修复区域的列冗余系统。通过列冗余系统，当修复区域被设置为分割位线时，修复区域被设置为使得可以一起被激活的多个字线属于同一修复区域。

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