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    • 1. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2014003095A
    • 2014-01-09
    • JP2012136260
    • 2012-06-15
    • Denso Corp株式会社デンソー
    • OKURA YASUTSUGU
    • H01L29/78G01K7/01H01L21/336H01L27/04
    • H01L24/33H01L2924/1305H01L2924/13055H01L2924/13091H01L2924/181H01L2924/351H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve temperature detection accuracy while inhibiting a short circuit.SOLUTION: A semiconductor device (10) comprises: a semiconductor substrate (20) on which an element is formed; an electrode (21) which is formed on a principal surface (20a) of the semiconductor substrate and electrically connected with the element; a temperature sensor (23) which is electrically independent from the electrode and formed on the principal surface side of the semiconductor substrate; and a first insulation film (25) formed on the principal surface with the temperature sensor covered so as to electrically insulate the temperature sensor with respect to solder (12) which is electrically connected with the electrode. The solder is arranged so as to cover at least a part of the temperature sensor. The semiconductor device includes a protection part (27) which has heat conductivity higher than that of air and inhibits stress caused by displacement of the solder from propagating to the first insulation film. The protection part is arranged to cover the first insulation film so as to be sandwiched between the solder and the first insulation film.
    • 要解决的问题:提供一种可以在抑制短路的同时提高温度检测精度的半导体器件。解决方案:半导体器件(10)包括:形成有元件的半导体衬底(20) 电极(21),其形成在所述半导体衬底的主表面(20a)上并与所述元件电连接; 温度传感器(23),其与所述电极电独立并且形成在所述半导体基板的所述主表面侧上; 以及第一绝缘膜(25),其形成在所述主表面上,所述温度传感器被覆盖以使得所述温度传感器相对于与所述电极电连接的焊料(12)电绝缘。 焊料布置成覆盖温度传感器的至少一部分。 半导体器件包括具有高于空气的导热性的保护部分(27),并且抑制由焊料的位移引起的应力传播到第一绝缘膜。 保护部件被布置成覆盖第一绝缘膜,以夹在焊料和第一绝缘膜之间。
    • 5. 发明专利
    • Semiconductor device, and inverter circuit using the same
    • 半导体器件和使用相同的反相器电路
    • JP2010087111A
    • 2010-04-15
    • JP2008252790
    • 2008-09-30
    • Denso Corp株式会社デンソー
    • OKURA YASUTSUGU
    • H01L25/07H01L25/18H02M7/48
    • H01L2224/48091H01L2224/48247H01L2224/73265H01L2924/1305H01L2924/13055H01L2924/30107H01L2924/00014H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a structure such that parasitic inductance is reduced when a semiconductor device is incorporated into an inverter circuit and an inspection at the final structure where the semiconductor device is incorporated into the inverter circuit is made possible, when the semiconductor device is inspected. SOLUTION: A first heat dissipation member 10 to be an N terminal is thermally and electrically connected to the top surface 13b of an IGBT chip 13, a second heat dissipation member 11 to be a P terminal is thermally and electrically connected to the reverse surface 14b of a diode chip 14, and a third heat dissipation member 12 to be an intermediate terminal is thermally and electrically connected to the reverse surface 13a of the IGBT chip 13 and the top surface 14a of the diode chip 14. Consequently, the reflow diode element of an upper arm 31 and the IGBT element of a lower arm 32 are connected in one semiconductor device without intervening of any other member. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了提供一种结构,使得当将半导体器件并入逆变器电路中时,寄生电感降低,并且使半导体器件结合到逆变器电路中的最终结构的检查成为可能,当 检查半导体器件。 解决方案:作为N端子的第一散热构件10热电连接到IGBT芯片13的顶面13b,作为P端子的第二散热构件11热电连接到 二极管芯片14的反面14b和作为中间端子的第三散热构件12热电连接到IGBT芯片13的反面13a和二极管芯片14的顶面14a。因此, 上臂31的回流二极管元件和下臂32的IGBT元件连接在一个半导体器件中,而不会插入任何其它元件。 版权所有(C)2010,JPO&INPIT
    • 6. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2010087110A
    • 2010-04-15
    • JP2008252788
    • 2008-09-30
    • Denso Corp株式会社デンソー
    • OKUMURA TOMOMIOKURA YASUTSUGU
    • H01L23/40
    • H01L2224/48091H01L2224/48247H01L2224/73265H01L2924/1305H01L2924/13055H01L2924/00014H01L2924/00
    • PROBLEM TO BE SOLVED: To improve the heat dissipation property of a double-sided heat dissipation semiconductor device without increasing the plane size of a heatsink. SOLUTION: A semiconductor device 100 includes a semiconductor element 1; heatsinks 2 and 3 electrically and thermally joined to the front surface and rear surface of the semiconductor element 1, respectively; and cooling devices 9 thermally joined to heat dissipation surfaces 2b and 3b of the heatsinks 2 and 3 which are surfaces opposite to the semiconductor element 1. A projected portion of the semiconductor element 1 on each heat dissipation surface 2b and 3b of each heatsink 2 and 3 is a convex portion 10 projecting toward the cooling devices 9 which face the heat dissipation surfaces 2b and 3b. Meanwhile, a portion of each cooling device 9 which faces the corresponding convex portion 10 is a concave portion 11. Each of the convex portions 10 is engaged with one of the concave portions 11. Between each of the convex portions 10 and one of the concave portions 11, an insulation film 12 is formed to electrically insulate the convex portion 10 and the concave portion 11. The convex portion 10 and the concave portion 11 are in contact with each other via the insulation film 12. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了提高双面散热半导体器件的散热性能,而不增加散热片的平面尺寸。 解决方案:半导体器件100包括半导体元件1; 散热片2和3分别电连接和热连接到半导体元件1的前表面和后表面; 以及与散热器2和3的与半导体元件1相对的表面的散热面2b和3b热连接的冷却装置9.半导体元件1在每个散热器2的每个散热表面2b和3b上的突出部分和 3是朝向散热面2b,3b的冷却装置9突出的凸部10。 同时,每个冷却装置9的与相应的凸部​​10相对的部分是凹部11.每个凸部10与凹部11中的一个接合。在每个凸部10和凹部 部分11,形成绝缘膜12以使凸部10和凹部11电绝缘。凸部10和凹部11经由绝缘膜12彼此接触。版权所有:(C )2010,JPO&INPIT
    • 7. 发明专利
    • Trench gate type semiconductor device and its manufacturing device
    • TRENCH门式半导体器件及其制造设备
    • JP2005045123A
    • 2005-02-17
    • JP2003279293
    • 2003-07-24
    • Denso CorpToyota Motor Corpトヨタ自動車株式会社株式会社デンソー
    • TAKATANI HIDESHIHAMADA KIMIMORIOKURA YASUTSUGUKUROYANAGI AKIRA
    • H01L29/41H01L21/336H01L29/417H01L29/78
    • PROBLEM TO BE SOLVED: To provide a trench gate type MOS FET of low ON resistance.
      SOLUTION: An n
      - -type drift region 2 and a p-channel region 3 are laminated one by one on an n
      + -type substrate 1. An n
      + -type source region 4 and a p
      + -type body region 5 are formed to a stripe in an upper surface of the p-channel region 3. A trench 7 passes through the p(n)-type channel region 3 and attains to the n
      - -type drift region 2, and a gate 9 constituted of polycrystalline silicon is buried via a gate insulating film 8. The n
      + -type source region 4 and the p
      + -type body region 5 extend from the p(n)-type channel region 3 to a source electrode 20 and cross the trench 7. The upper surface of the gate 9 is located above the upper surface of the p-channel region 3. A layer insulating film 10 is inside the trench 7, and its upper surface is located below an opening of the trench 7. The source electrode 20, the n
      + -type source region 4 and the p
      + -type body region 5 are electrically connected each in a side wall of the trench 7.
      COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:提供低导通电阻的沟槽栅型MOS FET。 解决方案:将n - / SP>型漂移区2和p沟道区3逐层层叠在n + 型衬底1上.n 在p沟道区域3的上表面中形成有条纹的 + 型源极区域4和ap + 型体区域5.沟槽7通过 p(n)型沟道区3并达到n - SP型漂移区2,并且由多晶硅构成的栅极9通过栅极绝缘膜8埋入。n + 型源极区域4和p + 型体区域5从p(n)型沟道区域3延伸到源电极20并与沟槽7交叉。 栅极9的上表面位于p沟道区域3的上表面之上。层间绝缘膜10位于沟槽7内,其上表面位于沟槽7的开口下方。源电极20 ,n + 型源区域4和p + 型体区域5分别电连接在一侧 沟槽的墙壁7.版权所有(C)2005,JPO&NCIPI
    • 9. 发明专利
    • 半導体装置
    • 半导体器件
    • JP2014241334A
    • 2014-12-25
    • JP2013122918
    • 2013-06-11
    • 株式会社デンソーDenso Corp富士電機株式会社Fuji Electric Co Ltd
    • SUGIURA SHUNOKURA YASUTSUGUFUJII TAKASHIIMAGAWA TETSUTARO
    • H01L21/822H01L21/3205H01L21/768H01L23/522H01L27/04H01L29/41H01L29/417
    • H01L23/562H01L23/34H01L23/4824H01L23/528H01L27/0255H01L29/417H01L2924/0002H01L2924/00
    • 【課題】表面電極と裏面電極がともにはんだ付けされる半導体装置において、反りを抑制しつつ、温度センサの温度検出精度の低下を抑制する。【解決手段】半導体装置(10)は、素子を有する半導体基板(12)と、半導体基板の表面上に設けられ、はんだ付けされる表面電極(18)と、半導体基板における表面と反対の裏面上に設けられ、はんだ付けされる裏面電極(14)と、半導体基板の表面上における分離領域(28)に設けられた保護膜(20)と、半導体基板の表面側に設けられた温度センサ(22)と、を備える。表面電極は、分離領域で、保護膜により、表面に沿う少なくとも2方向において複数に分割されている。分離領域は、分割されて互いに隣り合う表面電極の対向辺間に位置する対向領域(30)と、分離領域同士が交わる部分である交差領域(32)と、を含む。温度センサは、分離領域のうちの対向領域のみに配置されている。【選択図】図1
    • 要解决的问题:为了抑制温度传感器的温度检测精度的降低,同时抑制表面电极和背面电极两者焊接接合的半导体器件的翘曲。解决方案:半导体器件(10)包括:半导体衬底(12) )有一个元素 表面电极(18),其设置在所述半导体基板的表面上并焊接; 背面电极(14),设置在与表面相对的背面上,焊接接合; 设置在所述半导体衬底的表面上的隔离区域(28)中的保护膜(20) 以及设置在半导体基板的表面侧的温度传感器(22)。 表面电极通过保护膜沿着表面的隔离区域在至少两个方向上分成多个表面电极。 隔离区域包括位于表面电极的彼此分开和相邻的相对侧之间的相对区域(30)和作为隔离区域彼此交叉的部分的交叉区域(32)。 温度传感器仅布置在隔离区域中的相对区域中。
    • 10. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2014093486A
    • 2014-05-19
    • JP2012244712
    • 2012-11-06
    • Denso Corp株式会社デンソー
    • OKURA YASUTSUGU
    • H01L29/78H01L21/336H01L21/8234H01L27/04H01L27/06H01L27/088H01L29/739
    • H01L22/32G01R31/2621H01L22/14H01L27/088H01L29/0696H01L29/7397H01L2924/0002H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a semiconductor device that is able to restrict partial current concentration without using special tester in screening at high current density, and to provide an inspection method therefor.SOLUTION: A semiconductor device comprises: a semiconductor substrate (12) provided with a plurality of gate electrodes (26) arranged parallel to one another in a first direction and having a plurality of transistor cells (44) as cells (42) defined by adjacent gate electrodes; a gate wire (38) and a gate pad (36) that are formed on a first principal surface (12a) of a semiconductor substrate; a first pad (32) formed on the first principal surface and common to the plurality of transistor cells; and a second pad (40) formed on the first principal surface or a second principal surface (12b) and common to the transistor cells. A plurality of gate pads are provided, and gate electrodes are electrically separated into a plurality of types by the gate wires. Additionally, a plurality types of transistor cell are provided by combinations of defined gate electrodes.
    • 要解决的问题:提供一种在高电流密度下筛选时能够限制局部电流集中的半导体器件,并提供其检查方法。一种半导体器件,包括:半导体衬底(12) 设置有沿第一方向彼此平行布置的多个栅电极(26),并且具有作为由相邻栅电极限定的单元(42)的多个晶体管单元(44); 形成在半导体衬底的第一主表面上的栅极线(38)和栅极焊盘(36); 形成在所述第一主表面上并且与所述多个晶体管单元共用的第一焊盘(32) 以及形成在所述第一主表面上的第二焊盘(40)或所述晶体管单元共用的第二主表面(12b)。 提供多个栅极焊盘,并且栅电极通过栅极线电分离成多种类型。 此外,通过限定的栅电极的组合提供多种类型的晶体管单元。