专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4975882A User programmable redundant memory 失效
标题翻译：用户可编程冗余存储器
公开(公告)号：US4975882A
公开(公告)日：1990-12-04
申请号：US429956
申请日：1989-10-30
申请人： Clinton C. K. Kuo , Ernest A. Carter , Joseph Jelemensky
发明人： Clinton C. K. Kuo , Ernest A. Carter , Joseph Jelemensky
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A memory has a programmable circuit which allows a user to select an amount of redundancy the memory has varying from zero percent to one-hundred percent. A received address is compared by the circuit with a redundancy percentage control signal to determine if the address falls within a redundant portion of the memory. If so, a redundancy enable signal is asserted to allow the memory to utilize the redundant circuitry.
摘要翻译：存储器具有可编程电路，其允许用户选择存储器从0％变化到百分之百的冗余量。接收到的地址由电路与冗余百分比控制信号进行比较，以确定地址是否落在存储器的冗余部分内。如果是这样，则断言冗余使能信号以允许存储器利用冗余电路。

2. 发明授权

US5428574A Static RAM with test features 失效
标题翻译：具有测试功能的静态RAM
公开(公告)号：US5428574A
公开(公告)日：1995-06-27
申请号：US701536
申请日：1991-03-28
申请人： Clinton C. K. Kuo , Ernest A. Carter
发明人： Clinton C. K. Kuo , Ernest A. Carter
IPC分类号： G11C29/02 , G11C29/50 , G11C7/06
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50 , G11C29/50016 , G11C11/41 , G11C2029/5006
摘要： A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.
摘要翻译：静态RAM包括提供检测软缺陷的测试特征，这可能导致有缺陷的SRAM单元表现为功能性DRAM单元。提供写入高或低逻辑状态到SRAM的每个位线，而不向其互补位线写入任何值，并且用于独立于其互补位线的状态来感测每个位线的状态。此外，提供了通过由此引起的增加的逆变器漏电流来检测软缺陷的电流测试。通过适当组合这些测试，可以可靠地检测所有的软缺陷，从而保证SRAM的数据保留能力。该技术避免了现有技术中使用的长的保持时间和/或高温测试技术。

3. 发明授权

US5034923A Static RAM with soft defect detection 失效
标题翻译：具有软缺陷检测的静态RAM
公开(公告)号：US5034923A
公开(公告)日：1991-07-23
申请号：US283032
申请日：1988-12-05
申请人： Clinton C. K. Kuo , Ernest A. Carter
发明人： Clinton C. K. Kuo , Ernest A. Carter
IPC分类号： G11C29/02 , G11C29/50
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50 , G11C29/50016 , G11C11/41 , G11C2029/5006
摘要： A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.
摘要翻译：静态RAM包括提供检测软缺陷的测试特征，这可能导致有缺陷的SRAM单元表现为功能性DRAM单元。提供写入高或低逻辑状态到SRAM的每个位线，而不向其互补位线写入任何值，并且用于独立于其互补位线的状态来感测每个位线的状态。此外，提供了通过由此引起的增加的逆变器漏电流来检测软缺陷的电流测试。通过适当组合这些测试，可以可靠地检测所有的软缺陷，从而保证SRAM的数据保留能力。该技术避免了现有技术中使用的长的保持时间和/或高温测试技术。

4. 发明授权

US4547749A Voltage and temperature compensated FET ring oscillator 失效
标题翻译：电压和温度补偿FET环形振荡器
公开(公告)号：US4547749A
公开(公告)日：1985-10-15
申请号：US566608
申请日：1983-12-29
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： H03K3/011 , H03K3/354 , H03L1/02 , H03B5/00 , H03K3/26 , H03L1/00
CPC分类号： H03K3/011 , H03K3/3545 , H03L1/02
摘要： An oscillator with inverter and delay stages is coupled between first and second reference terminals. In one aspect a depletion transistor is connected between a power supply terminal and the first reference terminal to provide a reference voltage thereat. In another aspect the delay stages each have a control terminal for controlling the delay thereof. A temperature compensation circuit has a control transistor which provides a voltage to the control terminals of the delay stages which is inversely proportional to the threshold voltage of the control transistor.
摘要翻译：具有反相器和延迟级的振荡器耦合在第一和第二参考端子之间。在一个方面，耗尽晶体管连接在电源端子和第一参考端子之间以在其上提供参考电压。在另一方面，延迟级各自具有用于控制其延迟的控制端子。温度补偿电路具有控制晶体管，该控制晶体管向与控制晶体管的阈值电压成反比的延迟级的控制端提供电压。

5. 发明授权

US4459497A Sense amplifier using different threshold MOS devices 失效
标题翻译：感应放大器使用不同的阈值MOS器件
公开(公告)号：US4459497A
公开(公告)日：1984-07-10
申请号：US342040
申请日：1982-01-25
申请人： Clinton C. K. Kuo , Horst Leuschner
发明人： Clinton C. K. Kuo , Horst Leuschner
IPC分类号： G11C11/419 , H03K5/02 , H03K5/24 , G11C7/06
CPC分类号： H03K5/023
摘要： A sense amplifier quickly charges a column line to a first predetermined voltage level with first, second and third transistors and then charges the column to a second predetermined voltage by using only the second and third transistors. The second and third transistors continue charging to the second predetermined voltage by virtue of having a lower threshold voltage than the first transistor. If a selected memory cell in the column is in a conducting state, the column charges to only the first predetermined voltage for detection as a logic "0". If the selected memory cell in the column is in a non-conducting state, the column continues charging to the second predetermined voltage for detection as a logic "1".
摘要翻译：读出放大器利用第一，第二和第三晶体管将列线快速充电到第一预定电压电平，然后仅使用第二和第三晶体管将该列充电至第二预定电压。由于具有比第一晶体管低的阈值电压，第二和第三晶体管继续充电到第二预定电压。如果列中选定的存储单元处于导通状态，则该列仅将第一预定电压充电至逻辑“0”。如果列中所选择的存储单元处于非导通状态，则列继续充电到第二预定电压以作为逻辑“1”。

6. 发明授权

US5991201A Non-volatile memory with over-program protection and method therefor 失效
标题翻译：具有过程编程保护的非易失性存储器及其方法
公开(公告)号：US5991201A
公开(公告)日：1999-11-23
申请号：US067026
申请日：1998-04-27
申请人： Clinton C. K. Kuo , Thomas Jew , David W. Chrudimsky
发明人： Clinton C. K. Kuo , Thomas Jew , David W. Chrudimsky
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3486 , G11C16/3459 , G11C16/3468
摘要： A floating-gate non-volatile memory (30) uses a relatively-low threshold voltage to define a programmed state. The memory (30) compensates for fast program cells by providing program pulses which increase in length and magnitude while the cells are being programmed. Between each program pulse the memory (30) determines whether selected cells have been adequately programmed. The memory (30) ceases applying the series of pulses to each cell when it has been adequately programmed. Thus the memory (30) avoids the over-program condition instead of compensating for it.
摘要翻译：浮栅非易失性存储器（30）使用相对低的阈值电压来定义编程状态。存储器（30）通过提供在单元被编程时增加长度和幅度的编程脉冲来补偿快速编程单元。在每个编程脉冲之间，存储器（30）确定所选择的单元是否已被适当编程。当存储器（30）已被适当地编程时，存储器（30）停止向每个单元施加一系列脉冲。因此，存储器（30）避免了过程编程状态，而不是补偿它。

7. 发明授权

US5273923A Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions 失效
标题翻译：用于制造具有与场隔离区重叠的隧道开口的EEPROM单元的工艺
公开(公告)号：US5273923A
公开(公告)日：1993-12-28
申请号：US773791
申请日：1991-10-09
申请人： Ko-Min Chang , Clinton C. K. Kuo , Ming-Bing Chang
发明人： Ko-Min Chang , Clinton C. K. Kuo , Ming-Bing Chang
IPC分类号： G11C17/00 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/302 , H01L21/38 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/11524 , H01L29/7883
摘要： An EEPROM cell (10) has a tunnel opening (28) which overlaps both an active region (12) and field isolation regions (14). A tunnel area (30), which is that portion of the cell in which electrons tunnel through a tunnel dielectric (32) to charge or discharge a floating gate (22) during device operation, is defined as the overlapped portion of the tunnel opening (28) and the active region (12). By having the tunnel opening (28) larger than the tunnel area (30), etch processes used to pattern the opening in a gate dielectric (26) are more easily controlled and the active region area beneath the floating gate is reduced. The EEPROM cell (10) has a tunnel area which is limited in size by lithographic resolution capabilities rather than by limitations in dielectric etch processes. The tunnel features increase a capacitance coupling ratio of the cell.
摘要翻译： EEPROM单元（10）具有与有源区域（12）和场隔离区域（14）重叠的隧道开口（28）。隧道区域（30）是在设备操作期间电子穿过隧道电介质（32）充电或放电浮动栅极（22）的电池部分被定义为隧道开口的重叠部分（30） 28）和有源区（12）。通过使隧道开口（28）大于隧道区域（30），更容易控制用于对栅极电介质（26）中的开口进行图案化的蚀刻工艺，并且浮动栅极下方的有源区域面积减小。 EEPROM单元（10）具有通过光刻分辨能力限制尺寸的隧道区域，而不是通过电介质蚀刻工艺的限制。隧道特征增加了电池的电容耦合比。

8. 发明授权

US4408306A Column and row erasable EEPROM 失效
标题翻译：列和行可擦除EEPROM
公开(公告)号：US4408306A
公开(公告)日：1983-10-04
申请号：US306120
申请日：1981-09-28
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： G11C14/00 , G11C16/02 , G11C16/06 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/32 , G11C17/00 , G11C11/40
CPC分类号： G11C16/32 , G11C16/08 , G11C16/12 , G11C16/16
摘要： An EEPROM has an array of memory elements arranged by row and column which is accessed by a decoder capable of selecting all columns while enabling a single row in response to one input and selecting one column while enabling all rows in response to another input, thereby selectively erasing one entire row or column.
摘要翻译： EEPROM具有由行和列排列的存储器元件阵列，其由能够选择所有列的解码器访问，而能够响应于一个输入启用单个行并选择一列，同时响应于另一个输入启用所有行，从而选择性地擦除整个行或列。

9. 发明授权

US5130769A Nonvolatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US5130769A
公开(公告)日：1992-07-14
申请号：US700837
申请日：1991-05-16
申请人： Clinton C. K. Kuo , Ko-Min Chang
发明人： Clinton C. K. Kuo , Ko-Min Chang
IPC分类号： G11C17/00 , H01L21/8247 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42368 , H01L29/7885
摘要： A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and the remaining portion of the channel region forming an enhancement transistor. The second portion of the floating gate extends from the first portion over a thin oxide tunnel area of the source. An additional diode implant forming a junction with the drain region is provided to regulate the current flow through the drain, particularly during erasure.
摘要翻译：使用一个浮动栅极，它有两个部分。第一部分覆盖形成在源极和漏极之间的沟道区域。控制栅极覆盖浮置栅极的该部分，并且沟道区域的剩余部分形成增强晶体管。浮动栅极的第二部分从源极的薄氧化物隧道区域上的第一部分延伸。提供形成与漏极区的结的另外的二极管注入，以调节通过漏极的电流，特别是在擦除期间。

10. 发明授权

US4479203A Electrically erasable programmable read only memory cell 失效
标题翻译：电可擦除可编程只读存储单元
公开(公告)号：US4479203A
公开(公告)日：1984-10-23
申请号：US321855
申请日：1981-11-16
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： H01L27/112 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00 , G11C11/40
CPC分类号： H01L27/115 , G11C16/0433
摘要： An electrically erasable programmable read only memory (EEPROM) cell has a floating gate transistor and a select transistor in series. A control gate of the select transistor extends to an area which overlies an extended portion of a floating gate of the floating gate transistor to form an erase window so that the EEPROM cell can be erased by application of an erase signal to the control gate of the select transistor.
摘要翻译：电可擦除可编程只读存储器（EEPROM）单元具有串联的浮栅晶体管和选择晶体管。选择晶体管的控制栅极延伸到覆盖浮置晶体管的浮动栅极的延伸部分的区域，以形成擦除窗口，从而可以通过向擦除窗口的控制栅极施加擦除信号来擦除EEPROM单元选择晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式