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1. 发明申请

US20120264296A1 METHODS OF FORMING THROUGH SILICON VIA OPENINGS 有权
标题翻译：通过开口形成硅的方法
公开(公告)号：US20120264296A1
公开(公告)日：2012-10-18
申请号：US13086542
申请日：2011-04-14
申请人： Chyi Shyuan CHERN , Hsin-Hsien WU , Chun-Lin CHANG , Hsing-Kuo HSIA , Hung-Yi KUO
发明人： Chyi Shyuan CHERN , Hsin-Hsien WU , Chun-Lin CHANG , Hsing-Kuo HSIA , Hung-Yi KUO
IPC分类号： H01L21/768
CPC分类号： H01L21/76801 , H01L21/02057 , H01L21/3065 , H01L21/76898
摘要： A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical.
摘要翻译：形成贯通硅通孔（TSV）开口的方法包括通过基板形成TSV开口。使用第一种化学物质去除在TSV开口的侧壁上的衬底的材料的重铸。 TSV开口的侧壁通过基本上除去第一种化学物质的残留物而用第二种化学品清洗。

2. 发明申请

US20120104435A1 REFRACTIVE INDEX TUNING OF WAFER LEVEL PACKAGE LEDS 有权
标题翻译：水平包装LED的折射率调整
公开(公告)号：US20120104435A1
公开(公告)日：2012-05-03
申请号：US12912900
申请日：2010-10-27
申请人： Hsiao-Wen LEE , Shang-Yu TSAI , Tien-Ming LIN , Chyi Shyuan CHERN , Hsin-Hsien WU , Fu-Wen LIU , Huai-En LAI , Yu-Sheng TANG
发明人： Hsiao-Wen LEE , Shang-Yu TSAI , Tien-Ming LIN , Chyi Shyuan CHERN , Hsin-Hsien WU , Fu-Wen LIU , Huai-En LAI , Yu-Sheng TANG
IPC分类号： H01L33/50 , H01L23/24
CPC分类号： H01L33/54 , H01L33/44 , H01L33/504 , H01L33/507 , H01L33/56 , H01L2224/48091 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2933/005 , H01L2924/00 , H01L2924/00014
摘要： Two or more molded ellipsoid lenses are formed on a packaged LED die by injecting a glue material into a mold over the LED die and curing the glue material. After curing, the refractive index of the lens in contact with the LED die is greater than the refractive index of the lens not directly contacting the LED die. At least one phosphor material is incorporated into the glue material for at least one of the lenses not directly contacting the LED die. The lens directly contacting the LED die may also include one or more phosphor material. A high refractive index coating may be applied between the LED die and the lens.
摘要翻译：在封装的LED模具上形成两个或多个模制的椭圆体透镜，该胶片通过将胶料注入到LED模具中的模具中并固化胶料。固化后，与LED芯片接触的透镜的折射率大于不直接接触LED芯片的透镜的折射率。对于不直接接触LED管芯的透镜中的至少一个，将至少一种磷光体材料结合到胶合材料中。直接接触LED芯片的透镜还可以包括一种或多种荧光体材料。可以在LED管芯和透镜之间施加高折射率涂层。

3. 发明申请

US20120244652A1 METHODS OF FABRICATING LIGHT EMITTING DIODE DEVICES 有权
标题翻译：制造发光二极管器件的方法
公开(公告)号：US20120244652A1
公开(公告)日：2012-09-27
申请号：US13053701
申请日：2011-03-22
申请人： Yung-Chang CHEN , Hsin-Hsien WU , Chyi Shyuan CHERN , Ching-Wen HSIAO , Fu-Wen LIU , Kuang-Huan HSU
发明人： Yung-Chang CHEN , Hsin-Hsien WU , Chyi Shyuan CHERN , Ching-Wen HSIAO , Fu-Wen LIU , Kuang-Huan HSU
IPC分类号： H01L33/58
CPC分类号： H01L33/505 , H01L25/167 , H01L33/486 , H01L2224/16225 , H01L2224/48091 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2933/0041 , H01L2924/00014 , H01L2924/00
摘要： An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor.
摘要翻译：本公开的实施例包括制造多个发光二极管器件的方法。提供多个LED管芯。 LED管芯结合到载体衬底。包含多个开口的图案化掩模层形成在载体衬底上。多个LED管芯中的每一个分别通过多个开口中的一个露出。多个开口中的每一个都填充有荧光体。磷光体被固化。对磷光体和图案化掩模层进行抛光以使覆盖多个LED管芯中的每一个的磷光体变薄。在抛光荧光体之后去除图案化的掩模层。

4. 发明申请

US20130171803A1 METHOD FOR FABRICATING AN ISOLATION STRUCTURE 有权
标题翻译：制造隔离结构的方法
公开(公告)号：US20130171803A1
公开(公告)日：2013-07-04
申请号：US13775907
申请日：2013-02-25
申请人： Tze-Liang LEE , Pei-Ren JENG , Chu-Yun FU , Chyi Shyuan CHERN , Jui-Hei HUANG , Chih-Tang PENG , Hao-Ming LIEN
发明人： Tze-Liang LEE , Pei-Ren JENG , Chu-Yun FU , Chyi Shyuan CHERN , Jui-Hei HUANG , Chih-Tang PENG , Hao-Ming LIEN
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76232
摘要： A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
摘要翻译：一种制造隔离结构的方法，包括在衬底的顶表面中形成沟槽并用第一氧化物部分地填充沟槽，其中第一氧化物是纯氧化物。部分地填充沟槽包括在沟槽中形成衬层，并且在低于10毫托（mTorr）的压力和约500℃至约1000℃的温度下使用硅烷和氧前体在衬层上形成第一氧化物该方法还包括在第一氧化物的顶部产生固体反应产物。该方法还包括通过在室内在100℃至200℃的温度下加热基底来升华固体反应产物，并通过使载气流过基底而除去升华的固体反应产物。该方法还包括用第二氧化物填充沟槽。

5. 发明申请

US20100291751A1 METHOD FOR FABRICATING AN ISOLATION STRUCTURE 有权
标题翻译：制造隔离结构的方法
公开(公告)号：US20100291751A1
公开(公告)日：2010-11-18
申请号：US12774219
申请日：2010-05-05
申请人： Tze-Liang LEE , Pei-Ren JENG , Chu-Yun FU , Chyi Shyuan CHERN , Jui-Hei HUANG , Chih-Tang PENG , Hao-Ming LIEN
发明人： Tze-Liang LEE , Pei-Ren JENG , Chu-Yun FU , Chyi Shyuan CHERN , Jui-Hei HUANG , Chih-Tang PENG , Hao-Ming LIEN
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76232
摘要： The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.
摘要翻译：本发明涉及集成电路制造，更具体地说涉及具有几乎没有空隙的隔离结构的电子器件。一种用于制造隔离结构的示例性方法，包括：提供衬底; 在衬底中形成沟槽; 用第一氧化硅部分地填充沟槽; 将第一氧化硅的表面暴露于包含NH 3和含氟化合物的蒸汽混合物中; 将基板加热至100℃至200℃的温度; 并用第二氧化硅填充沟槽，由此所制成的隔离结构几乎没有空隙。

6. 发明申请

US20120086075A1 DEVICE WITH ALUMINUM SURFACE PROTECTION 有权
标题翻译：具有铝表面保护的器件
公开(公告)号：US20120086075A1
公开(公告)日：2012-04-12
申请号：US13327992
申请日：2011-12-16
申请人： Kuo Bin HUANG , Ssu-Yi LI , Ryan Chia-Jen CHEN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
发明人： Kuo Bin HUANG , Ssu-Yi LI , Ryan Chia-Jen CHEN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
IPC分类号： H01L27/088
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L21/28247 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer.
摘要翻译：具有金属栅极结构的半导体结构包括具有第一栅极的第一型场效应晶体管，包括：基板上的高k电介质材料，高k电介质材料层上的第一金属层，具有第一功函数，以及在第一金属层上的第一铝层。第一铝层包括包含铝，氮和氧的界面层。该器件还包括具有第二栅极的第二类场效应晶体管，其包括：衬底上的高k电介质材料，高k电介质材料层上的第二金属层，具有不同于第一功函数的第二功函数，和在第二金属层上的第二铝层。

7. 发明申请

US20120064715A1 INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION 有权
标题翻译：底部金属膜沉积的整合
公开(公告)号：US20120064715A1
公开(公告)日：2012-03-15
申请号：US13302520
申请日：2011-11-22
申请人： Simon Su-Horng LIN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
发明人： Simon Su-Horng LIN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
IPC分类号： H01L21/26
CPC分类号： H01L29/78 , C23C14/022 , C23C14/046 , C23C14/18 , C23C14/221 , C23C16/0263 , C23C16/045 , C23C16/06 , C23C16/48 , C23C16/484 , H01L21/28079 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76856 , H01L21/76862 , H01L21/76865 , H01L21/76877 , H01L29/4966 , H01L29/66545
摘要： A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up.
摘要翻译：在具有图案特征的基板上沉积金属膜的方法包括将具有图案化特征的基板放置在光致化学气相沉积（PI-CVD）处理室中。该方法还包括通过PI-CVD沉积金属膜以从下向上填充图案化特征。

8. 发明申请

US20100291840A1 SYSTEM AND METHOD FOR CONDITIONING CHEMICAL MECHANICAL POLISHING APPARATUS USING MULTIPLE CONDITIONING DISKS 审中-公开
标题翻译：使用多个调节盘调节化学机械抛光装置的系统和方法
公开(公告)号：US20100291840A1
公开(公告)日：2010-11-18
申请号：US12464223
申请日：2009-05-12
申请人： Soon Kang HUANG , Kun-Ku HUNG , Zin-Chang WEI , Chyi Shyuan CHERN
发明人： Soon Kang HUANG , Kun-Ku HUNG , Zin-Chang WEI , Chyi Shyuan CHERN
IPC分类号： B24B1/00 , B24B7/07
CPC分类号： B24B53/003 , B24B53/017
摘要： A chemical mechanical polishing (CMP) apparatus provides for polishing semiconductor wafers and for conditioning the polishing pad of the CMP apparatus using multiple conditioning disks at the same time. The conditioning disks may be moved together or independently along the surface of polishing pad to condition the entire surface of the rotating polishing pad.
摘要翻译：化学机械抛光（CMP）装置提供用于抛光半导体晶片并且同时使用多个调节盘来调节CMP设备的抛光垫。调理盘可以沿着抛光垫的表面一起移动或独立地移动，以调节旋转抛光垫的整个表面。

9. 发明申请

US20100267172A1 Formation of Shallow Trench Isolation Using Chemical Vapor Etch 有权
标题翻译：使用化学蒸气蚀刻法形成浅沟槽隔离
公开(公告)号：US20100267172A1
公开(公告)日：2010-10-21
申请号：US12426711
申请日：2009-04-20
申请人： Ying XIAO , Chyi Shyuan CHERN
发明人： Ying XIAO , Chyi Shyuan CHERN
IPC分类号： H01L21/66 , C23F1/08
CPC分类号： H01L22/20 , H01L21/76224 , H01L22/12
摘要： A method includes measuring a depth of a shallow trench isolation (STI) region below a surface of a substrate. The STI region is filled with an oxide material. The substrate has a nitride layer above the surface. A thickness of the nitride layer is measured. A first chemical vapor etch (CVE) of the oxide material is performed, to partially form a recess in the STI region. The first CVE removes an amount of the oxide material less than the thickness of the nitride layer. The nitride layer is removed by dry etching. A remaining height of the STI region is measured after removing the nitride. A second CVE of the oxide material in the STI region is performed, based on the measured depth and the remaining height, to form at least one fin having a desired fin height above the oxide in the STI region without an oxide fence.
摘要翻译：一种方法包括测量衬底表面下面的浅沟槽隔离（STI）区域的深度。 STI区域填充有氧化物材料。衬底在表面上方具有氮化物层。测量氮化物层的厚度。执行氧化物材料的第一化学气相蚀刻（CVE），以在STI区域中部分地形成凹陷。第一CVE去除少于氮化物层的厚度的一定量的氧化物材料。通过干蚀刻去除氮化物层。在去除氮化物之后测量STI区的剩余高度。基于测量的深度和剩余高度，执行STI区域中的氧化物材料的第二CVE，以形成在没有氧化物栅栏的STI区域中具有高于氧化物的所需翅片高度的至少一个翅片。

10. 发明申请

US20110086504A1 METHODS FOR FORMING INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路的方法
公开(公告)号：US20110086504A1
公开(公告)日：2011-04-14
申请号：US12879371
申请日：2010-09-10
申请人： Kuo Bin HUANG , Hsin-Chien LU , Ryan Chia-Jen CHEN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
发明人： Kuo Bin HUANG , Hsin-Chien LU , Ryan Chia-Jen CHEN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
IPC分类号： H01L21/3205 , H01L21/302
CPC分类号： H01L21/28238 , H01L21/02071 , H01L21/823842 , H01L21/823857
摘要： A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed.
摘要翻译：提供一种用于形成集成电路的方法。该方法包括在衬底上形成栅极电介质结构。形成与该栅电介质结构接触的含钛牺牲层。基本上除去了整个含钛牺牲层。

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