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1. 发明申请

US20060220181A1 Controllable varactor within dummy substrate pattern 有权
公开(公告)号：US20060220181A1
公开(公告)日：2006-10-05
申请号：US11097743
申请日：2005-04-01
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Yuan Lin
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Yuan Lin
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L27/0808 , H01L29/417
摘要： A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures disposed in the dummy region defining adjacent mesa regions comprising first, second, and third mesa regions; a second well region having a second polarity underlying the first mesa region having the second polarity to form a PN junction interface; wherein said second and third mesa regions having the first polarity are formed adjacent either side of said first mesa region.

2. 发明授权

US07525177B2 Controllable varactor within dummy substrate pattern 有权
标题翻译：虚拟衬底图案中的可控变容二极管
公开(公告)号：US07525177B2
公开(公告)日：2009-04-28
申请号：US11097743
申请日：2005-04-01
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Yuan Lin
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Yuan Lin
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L27/0808 , H01L29/417
摘要： A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures disposed in the dummy region defining adjacent mesa regions comprising first, second, and third mesa regions; a second well region having a second polarity underlying the first mesa region having the second polarity to form a PN junction interface; wherein said second and third mesa regions having the first polarity are formed adjacent either side of said first mesa region.
摘要翻译：一种用于改善CMP工艺并改善与有源区的电隔离的虚拟区域变容二极管及其形成方法，所述变容二极管包括具有虚拟区域的半导体衬底，所述虚拟区域包括具有第一极性的第一阱区; 布置在所述虚拟区域中的浅沟槽隔离（STI）结构，其限定包括第一，第二和第三台面区域的相邻台面区域; 具有第二极性的第二阱区，其具有第二极性的第一台面区域，以形成PN结界面; 其中具有第一极性的所述第二和第三台面区域形成在所述第一台面区域的两侧附近。

3. 发明授权

US08174091B2 Fuse structure 有权
标题翻译：保险丝结构
公开(公告)号：US08174091B2
公开(公告)日：2012-05-08
申请号：US12503641
申请日：2009-07-15
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

4. 发明授权

US08153498B2 Downsize polysilicon height for polysilicon resistor integration of replacement gate process 有权
标题翻译：多晶硅电阻尺寸缩小，替代栅极工艺集成
公开(公告)号：US08153498B2
公开(公告)日：2012-04-10
申请号：US12401876
申请日：2009-03-11
申请人： Chen-Pin Hsu , Chung-Long Cheng , Kong-Beng Thei , Harry Chuang
发明人： Chen-Pin Hsu , Chung-Long Cheng , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8232
CPC分类号： H01L27/0629 , H01L21/82345 , H01L27/088 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.
摘要翻译：公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

5. 发明授权

US07768069B2 FIN-FET device structure 有权
标题翻译： FIN-FET器件结构
公开(公告)号：US07768069B2
公开(公告)日：2010-08-03
申请号：US11334974
申请日：2006-01-18
申请人： Chung-Long Cheng , Kong-Beng Thei
发明人： Chung-Long Cheng , Kong-Beng Thei
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/785 , H01L21/32139 , H01L29/42384 , H01L29/66795
摘要： A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.
摘要翻译：用于形成FIN-FET器件的方法使用形成在覆盖的地形栅电极材料层上的覆盖平坦化层。图案化覆盖层平坦化层并用作掩模层，用于图案化覆盖层形成的栅电极材料层以形成栅电极。由于覆盖平坦化层形成为平坦化层，所以在其上形成的光致抗蚀剂层以更高的分辨率形成。结果，栅电极也形成了增强的分辨率。所得到的FIN-FET结构具有在栅电极上以倒U形形成的图案化平坦化层。

6. 发明授权

US07632729B2 Method for semiconductor device performance enhancement 有权
标题翻译：半导体器件性能提高的方法
公开(公告)号：US07632729B2
公开(公告)日：2009-12-15
申请号：US11527616
申请日：2006-09-27
申请人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/7843
摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.
摘要翻译：公开了制造半导体器件的方法。该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。在NMOS和PMOS器件上形成第一绝缘层。在第一绝缘层上形成第二绝缘层。覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。在NMOS和PMOS器件上进行第一次热处理。去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

7. 发明申请

US20090218623A1 SOI DEVICES AND METHODS FOR FABRICATING THE SAME 有权
公开(公告)号：US20090218623A1
公开(公告)日：2009-09-03
申请号：US12468137
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

8. 发明授权

US07550795B2 SOI devices and methods for fabricating the same 有权
标题翻译： SOI器件及其制造方法
公开(公告)号：US07550795B2
公开(公告)日：2009-06-23
申请号：US11477953
申请日：2006-06-30
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L29/76
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

9. 发明申请

US20080315320A1 Semiconductor Device with both I/O and Core Components and Method of Fabricating Same 有权
标题翻译：具有I / O和核心组件的半导体器件及其制造方法
公开(公告)号：US20080315320A1
公开(公告)日：2008-12-25
申请号：US11766425
申请日：2007-06-21
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
IPC分类号： H01L29/76 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

10. 发明申请

US20080296691A1 Layout methods of integrated circuits having unit MOS devices 有权
标题翻译：具有单位MOS器件的集成电路的布局方法
公开(公告)号：US20080296691A1
公开(公告)日：2008-12-04
申请号：US11807654
申请日：2007-05-30
申请人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
IPC分类号： H01L29/76
CPC分类号： H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
摘要翻译：半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

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