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1. 发明申请

US20110291197A1 INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20110291197A1
公开(公告)日：2011-12-01
申请号：US12787966
申请日：2010-05-26
申请人： Chung-Cheng WU , Ali KESHAVARZI , Ka Hing FUNG , Ta-Pen GUO , Jiann-Tyng TZENG , Yen-Ming CHEN , Shyue-Shyh LIN , Shyh-Wei WANG , Sheng-Jier YANG , Hsiang-Jen TSENG , David B. SCOTT , Min CAO
发明人： Chung-Cheng WU , Ali KESHAVARZI , Ka Hing FUNG , Ta-Pen GUO , Jiann-Tyng TZENG , Yen-Ming CHEN , Shyue-Shyh LIN , Shyh-Wei WANG , Sheng-Jier YANG , Hsiang-Jen TSENG , David B. SCOTT , Min CAO
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L27/092 , H01L29/7848 , H01L2224/16225
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域间隔开。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属层与第一源区电耦合。第一金属层和第一扩散区域与第一距离重叠。第二金属层与第一漏极区域和第二漏极区域电耦合。第二金属层和第一扩散区域与第二距离重叠。第一距离大于第二距离。

2. 发明申请

US20130130456A1 INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20130130456A1
公开(公告)日：2013-05-23
申请号：US13722142
申请日：2012-12-20
申请人： Chung-Cheng WU , Ali KESHAVARZI , Fung Ka HING , Ta-Pen GUO , Jiann-Tyng TZENG , Yen-Ming CHEN , Shyue-Shyh LIN , Shyh-Wei WANG , Sheng-Jier YANG , Hsiang-Jen TSENG , David B. Scott , Min CAO
发明人： Chung-Cheng WU , Ali KESHAVARZI , Fung Ka HING , Ta-Pen GUO , Jiann-Tyng TZENG , Yen-Ming CHEN , Shyue-Shyh LIN , Shyh-Wei WANG , Sheng-Jier YANG , Hsiang-Jen TSENG , David B. Scott , Min CAO
IPC分类号： H01L29/66
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L27/092 , H01L29/7848 , H01L2224/16225
摘要： A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.
摘要翻译：一种形成集成电路的方法，包括在衬底上形成第一扩散区域和第二扩散区域，其中所述第一扩散区域被配置为用于第一类型晶体管，所述第二扩散区域被配置为用于第二类型晶体管。该方法还包括在第一扩散区域中形成第一源区和漏区。该方法还包括在第二扩散区域中形成第二源区和漏区。该方法还包括形成跨越第一扩散区域和第二扩散区域延伸的栅电极。该方法还包括形成第一金属层，第二金属层和第三金属层。第一金属层与第一源区电耦合。第二金属层与第一和第二漏极区域电耦合。第三金属层与第二源极区域电耦合。

3. 发明申请

US20110291200A1 INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20110291200A1
公开(公告)日：2011-12-01
申请号：US13086186
申请日：2011-04-13
申请人： Ali KESHAVARZI , Ta-Pen GUO , Helen Shu-Hui CHANG , Hsiang-Jen TSENG , Shyue-Shyh LIN , Lee-Chung LU , Chung-Cheng WU , Li-Chun TIEN , Jung-Chan YANG , Shu-Min CHEN , Min CAO , Yung-Chin HOU
发明人： Ali KESHAVARZI , Ta-Pen GUO , Helen Shu-Hui CHANG , Hsiang-Jen TSENG , Shyue-Shyh LIN , Lee-Chung LU , Chung-Cheng WU , Li-Chun TIEN , Jung-Chan YANG , Shu-Min CHEN , Min CAO , Yung-Chin HOU
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

4. 发明申请

US20120266110A1 DUAL-PATTERN COLORING TECHNIQUE FOR MASK DESIGN 有权
标题翻译：双色图案彩色设计技术
公开(公告)号：US20120266110A1
公开(公告)日：2012-10-18
申请号：US13087324
申请日：2011-04-14
申请人： Min CAO , Jeffrey MARKHAM
发明人： Min CAO , Jeffrey MARKHAM
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/68 , G03F1/70
摘要： A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.
摘要翻译：分层示意图设计编辑器将每个形状的掩模层显示为掩模特定颜色，并提醒用户在设计和编辑过程中屏蔽层冲突。根据实施例，可以在形状或几何形状和单元被放置在电路设计布局中时，或者当指示将两个或多个形状设置为不同掩模层的掩模层条件时，可以分配掩模颜色。在一个实施例中，如果两个形状之间的距离小于预定阈值，则这些形状可能导致掩模层条件。形状可以被分组以便于掩模层条件检测和掩模层分配。

5. 发明申请

US20120100681A1 METHOD OF MANUFACTURING SOURCE/DRAIN STRUCTURES 有权
标题翻译：制造源/排水结构的方法
公开(公告)号：US20120100681A1
公开(公告)日：2012-04-26
申请号：US12981610
申请日：2010-12-30
申请人： Ziwei FANG , Jeff J. XU , Ming-Jie HUANG , Yimin HUANG , Zhiqiang WU , Min CAO
发明人： Ziwei FANG , Jeff J. XU , Ming-Jie HUANG , Yimin HUANG , Zhiqiang WU , Min CAO
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/02057 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/30604 , H01L21/30608 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.
摘要翻译：用于制造集成电路器件的集成电路器件和方法通过在第一掺杂区域中形成第二掺杂区域并且去除第一和第二掺杂区域，从而提供对用于形成集成电路器件的源极和漏极特征的沟槽形状的改进的控制第二掺杂区域通过第一和第二湿蚀刻工艺。

6. 发明申请

US20100283109A1 MOSFET HAVING A CHANNEL MECHANICALLY STRESSED BY AN EPITAXIALLY GROWN, HIGH K STRAIN LAYER 有权
标题翻译：具有由外延生长的高K应变层受力的通道的MOSFET
公开(公告)号：US20100283109A1
公开(公告)日：2010-11-11
申请号：US12839468
申请日：2010-07-20
申请人： Min CAO
发明人： Min CAO
IPC分类号： H01L29/78
CPC分类号： H01L29/513 , H01L21/02175 , H01L21/28194 , H01L21/3147 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L21/3185 , H01L29/517 , H01L29/7843
摘要： A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material.
摘要翻译：具有设置在衬底的通道区域上方的外延生长的应变层的晶体管，这种晶体管用于强调沟道区域以增加沟道中的载流子迁移率，以及制造其的方法。应变层由高介电常数材料构成。

7. 发明申请

US20110219341A1 METHOD, SYSTEM, AND PROGRAM PRODUCT FOR INTERACTIVE CHECKING FOR DOUBLE PATTERN LITHOGRAPHY VIOLATIONS 有权
标题翻译：用于双重图案破译的交互式检查的方法，系统和程序产品
公开(公告)号：US20110219341A1
公开(公告)日：2011-09-08
申请号：US12719710
申请日：2010-03-08
申请人： Min CAO , Roland RUEHL
发明人： Min CAO , Roland RUEHL
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.
摘要翻译：公开了一种用于执行交互式布局编辑以解决实现电子设计的光刻的双重图案化方法的方法，装置和计算机程序产品。在编辑期间创建的形状周围执行空间查询，其中单个掩码中允许的间距距离。如果遇到设计错误，可能会进行纠正编辑，以纠正错误。可能会发生检查，以确保可以交互式执行错误检测和纠正措施。

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