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1. 发明授权

US08804430B2 Selected word line dependent select gate diffusion region voltage during programming 有权
标题翻译：选择字线依赖选择栅扩散区电压编程
公开(公告)号：US08804430B2
公开(公告)日：2014-08-12
申请号：US13430494
申请日：2012-03-26
申请人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

2. 发明申请

US20130250689A1 SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMMING 有权
标题翻译：在编程期间选择的字线相关选择门限扩展区域电压
公开(公告)号：US20130250689A1
公开(公告)日：2013-09-26
申请号：US13430494
申请日：2012-03-26
申请人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

3. 发明申请

US20130250690A1 SELECTED WORD LINE DEPENDENT SELECT GATE VOLTAGE DURING PROGRAM 有权
标题翻译：在程序期间选择的字线相关选择门电压
公开(公告)号：US20130250690A1
公开(公告)日：2013-09-26
申请号：US13430502
申请日：2012-03-26
申请人： Chun-Hung Lai , Deepanshu Dutta , Shinji Sato , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Deepanshu Dutta , Shinji Sato , Gerrit Jan Hemink
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于选择用于编程的字线的位置，这可以减少或消除程序干扰。施加到NAND串的选择晶体管的栅极的电压可以取决于所选字线的位置。这可以是源极侧或漏极侧选择晶体管。这可能会阻止或减少由于DIBL而导致的程序干扰。这也可以防止或减少由于GIDL可能导致的程序干扰。当编程至少一些字线时，负偏压可以施加到源极侧选择晶体管的栅极。在一个实施例中，当编程逐渐增加的字线时，逐渐降低的电压用于漏极侧选择晶体管的栅极。

4. 发明授权

US08638608B2 Selected word line dependent select gate voltage during program 有权
标题翻译：程序中所选字线相关选择栅极电压
公开(公告)号：US08638608B2
公开(公告)日：2014-01-28
申请号：US13430502
申请日：2012-03-26
申请人： Chun-Hung Lai , Deepanshu Dutta , Shinji Sato , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Deepanshu Dutta , Shinji Sato , Gerrit Jan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于选择用于编程的字线的位置，这可以减少或消除程序干扰。施加到NAND串的选择晶体管的栅极的电压可以取决于所选字线的位置。这可以是源极侧或漏极侧选择晶体管。这可能会阻止或减少由于DIBL而导致的程序干扰。这也可以防止或减少由于GIDL可能导致的程序干扰。当编程至少一些字线时，负偏压可以施加到源极侧选择晶体管的栅极。在一个实施例中，当编程逐渐增加的字线时，逐渐降低的电压用于漏极侧选择晶体管的栅极。

5. 发明申请

US20120300550A1 Ramping Pass Voltage To Enhance Channel Boost In Memory Device, With Optional Temperature Compensation 有权
标题翻译：缓存通过电压，以增强存储器件中的通道升压，具有可选的温度补偿
公开(公告)号：US20120300550A1
公开(公告)日：2012-11-29
申请号：US13113786
申请日：2011-05-23
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/10
摘要： In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.
摘要翻译：在非易失性存储系统中，用于未选择的NAND串的一个或多个衬底沟道区在编程期间升高以抑制编程干扰。在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到与至少第一信道区域相关联的一个或多个未选择字线的电压增加。增加可以是渐进的，以斜坡的形式，或逐步的。可以维持第一通道区域的升压水平。施加到一个或多个未选择字线的电压的增加也随着温度而变化。在编程脉冲时间段之前，施加到一个或多个未选择字线的电压可以以比第一通道区域更快的速率向第二相邻通道区域上升，以帮助隔离通道区域。

6. 发明授权

US08189378B2 Reducing program disturb in non-volatile storage 有权
标题翻译：在非易失性存储中减少程序干扰
公开(公告)号：US08189378B2
公开(公告)日：2012-05-29
申请号：US11535628
申请日：2006-09-27
申请人： Gerrit Jan Hemink , Shih-Chung Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C7/1006 , G11C11/5628 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C2211/5621
摘要： A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected to non-volatile storage elements that may be partially programmed.
摘要翻译：非易失性半导体存储系统被编程为通过在连接到可以被部分编程的非易失性存储元件的一个或多个字线上施加更高的升压电压来减少编程干扰。

7. 发明申请

US20110235423A1 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US20110235423A1
公开(公告)日：2011-09-29
申请号：US13154810
申请日：2011-06-07
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

8. 发明授权

US07978527B2 Verification process for non-volatile storage 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US07978527B2
公开(公告)日：2011-07-12
申请号：US12132452
申请日：2008-06-03
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

9. 发明申请

US20100149881A1 ADAPTIVE ERASE AND SOFT PROGRAMMING FOR MEMORY 有权
标题翻译：自适应删除和软件编程存储器
公开(公告)号：US20100149881A1
公开(公告)日：2010-06-17
申请号：US12332646
申请日：2008-12-11
申请人： Shih-Chung Lee , Gerrit Jan Hemink
发明人： Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/16 , G11C16/3404
摘要： An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration.
摘要翻译：非易失性存储设备的擦除序列包括随后进行软编程操作的擦除操作。擦除操作例如经由衬底将一个或多个擦除脉冲施加到存储元件，直到满足擦除验证电平。跟踪和记录擦除脉冲的数量作为存储设备经历的编程擦除周期数的标记。软编程操作将软编程脉冲应用于存储元件，直到满足软编程验证电平。基于擦除脉冲的数量，通过跳过针对擦除脉冲数的函数的特定数量的初始软编程脉冲的验证操作来缩短软编程操作时间。此外，可以优化软编程操作的特性，例如起始幅度，步长或脉冲持续时间。

10. 发明申请

US20080084747A1 REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE 有权
标题翻译：减少非挥发性储存中的程序干扰
公开(公告)号：US20080084747A1
公开(公告)日：2008-04-10
申请号：US11535628
申请日：2006-09-27
申请人： Gerrit Jan Hemink , Shih-Chung Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee
IPC分类号： G11C16/04 , G11C7/00 , G11C11/34
CPC分类号： G11C16/0483 , G11C7/1006 , G11C11/5628 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C2211/5621
摘要： A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile storage elements that may be partially programmed.
摘要翻译：非易失性半导体存储系统以通过在可以被部分编程的连接的非易失性存储元件的一个或多个字线上施加更高的升压电压来减少编程干扰的方式进行编程。

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