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1. 发明授权

US5998826A Triple well floating gate memory and operating method with isolated channel program, preprogram and erase processes 失效
标题翻译：三通井浮动存储器和具有隔离通道程序，预编程和擦除过程的操作方法
公开(公告)号：US5998826A
公开(公告)日：1999-12-07
申请号：US817656
申请日：1997-04-04
申请人： Chun-Hsiung Hung , Tzeng-Huei Shiau , Ray-Lin Wan , Fu-Chia Shone
发明人： Chun-Hsiung Hung , Tzeng-Huei Shiau , Ray-Lin Wan , Fu-Chia Shone
IPC分类号： G11C16/16 , H01L29/788 , H01L27/76
CPC分类号： G11C16/16
摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows Fowler Nordheim (F-N) tunneling with lower absolute value bias potentials. Thus, the floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well. Also, circuits are coupled with the cell to induce hot electron injection current of electrons into the floating gate for programming or byte by byte preprogramming.
摘要翻译： PCT No.PCT / US96 / 14349 Sec。 371日期1997年04月4日 102（e）日期1997年4月4日PCT 1996年9月5日PCT公布。公开号WO98 / 10471 日期1998年3月12日新的闪存单元结构和操作偏置基于使用三阱闪存单元，这允许具有较低绝对值偏置电位的Fowler Nordheim（F-N）隧穿。因此，浮置栅极存储单元被制成具有第一导电类型的诸如p型的半导体衬底。包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。还包括第一阱中的第二阱具有第一导电类型。在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。通道区域中包括浮动栅极和控制栅极结构。浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。块宽预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。此外，电路与电池耦合以将电子的热电子注入电流引入浮动栅极进行编程或逐字节预编程。

2. 发明授权

US5818764A Block-level wordline enablement to reduce negative wordline stress 失效
标题翻译：块级字词启用以减少负面字线压力
公开(公告)号：US5818764A
公开(公告)日：1998-10-06
申请号：US796821
申请日：1997-02-06
申请人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C16/16 , G11C16/00
CPC分类号： G11C8/08 , G11C16/08 , G11C16/16
摘要： A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.
摘要翻译：提供电路，用于向浮动栅极存储单元阵列中的选定块的字线提供负的擦除电压。该电路包括具有多个本地输出的电压电路，每个本地输出连接到浮动栅极存储器单元的相关块的字线。块选择器电路耦合到电压电路的本地输出，并且选择性地切换每个本地输出以将擦除电压或非擦除电压施加到浮动栅极存储器单元的相关联块的字线上。因此，对于在块擦除操作期间接收到较小负的非擦除电压的未选择块的字线，负字线应力减小。

3. 发明授权

US5699298A Flash memory erase with controlled band-to-band tunneling current 失效
标题翻译：具有受控的带对隧道电流的闪存擦除
公开(公告)号：US5699298A
公开(公告)日：1997-12-16
申请号：US718525
申请日：1996-10-07
申请人： Tzeng-Huei Shiau , Ray-Lin Wan , Yuan-Chang Liu , Chun-Hsiung Hung , Weitong Chuang , Han Sung Chen , Fuchia Shone
发明人： Tzeng-Huei Shiau , Ray-Lin Wan , Yuan-Chang Liu , Chun-Hsiung Hung , Weitong Chuang , Han Sung Chen , Fuchia Shone
IPC分类号： G11C16/16 , G11C16/30 , G11C16/00
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/30
摘要： Substantial reduction in peak current encountered during an erase process for a flash memory device is achieved by selection of source voltage potential during the erase according to the expected band-to-band tunneling current encountered during the process. During the beginning of the process, a lower source voltage potential is selected, which is high enough to cause significant erasing while suppressing band-to-band tunneling current in a portion of the array, and during a second part of the erasing process, a higher source potential is utilized, which ensures successful erasing of the array, without exceeding the peak current requirements of the power supply used with the device. The first and second parts of the erase sequence will induce band-to-band tunneling current in addition to Fowler-Nordheim tunneling current. The band-to-band tunneling current is characterized by a turn on threshold source potential which is inversely related to the threshold of the cell receiving the voltage sequence. The source voltage used in the first part of the erase sequence is set at level that is near or above the turn on threshold source potential for higher threshold cells that are in the high threshold state, but less than the turn on threshold source potential for lower threshold cells in the high threshold state. The source potential in the second part is set at level which is near or above the turn on threshold source potential for lower threshold cells in the high threshold state.
摘要翻译： PCT No.PCT / US96 / 07490 Sec。 371日期1996年10月7日第 102（e）1996年10月7日PCT 1996年5月22日提交闪速存储器件的擦除过程中遇到的峰值电流的实质性降低是通过根据预期的带 - 带来在擦除期间选择源极电压电位来实现的过程中遇到的隧道电流。在该过程开始时，选择较低的源极电压电位，其足够高以引起显着擦除，同时抑制阵列的一部分中的带间隧穿电流，并且在擦除处理的第二部分期间，利用更高的源极电位，确保阵列的成功擦除，而不超过与器件一起使用的电源的峰值电流要求。擦除序列的第一部分和第二部分除了Fowler-Nordheim隧道电流之外还将引起带间隧穿电流。带 - 带隧穿电流的特征在于开启阈值源极电位，其与接收电压序列的电池的阈值成反比。在擦除序列的第一部分中使用的源电压被设置为接近或高于处于高阈值状态的较高阈值电池的阈值源极电位的接通或高于电平，但小于阈值源电位的导通电平较低阈值细胞处于高阈值状态。第二部分中的源极电位被设置在接近或高于阈值电位的阈值源电位的接通或高于在高阈值状态下的较低阈值电池的电位。

4. 发明授权

US6087190A Automatic test process with non-volatile result table store 失效
标题翻译：自动测试过程与非易失性结果表存储
公开(公告)号：US6087190A
公开(公告)日：2000-07-11
申请号：US973582
申请日：1997-11-17
申请人： Ray-Lin Wan , Chun-Hsiung Hung , Tzeng-Huei Shiau
发明人： Ray-Lin Wan , Chun-Hsiung Hung , Tzeng-Huei Shiau
IPC分类号： G11C29/24 , G11C29/44 , H10L21/00 , G01R31/26 , H10L21/66
CPC分类号： G11C29/24 , G11C29/44
摘要： A method of manufacturing integrated circuits based on providing a test column of memory cells in the devices. Cells in the test column are selected by a portion of the addresses which identifies a row in the main array on the device. A test is executed to determine a characteristic of the device, and the results of that test are mapped to the portion of the address which identifies a row in the array. This produces a characteristic code address for the device which indicates the results of the test. Access to the test column on the device is enabled, and a bit is written in response to the characteristic code address in a memory cell on the test column. During manufacture the test column is read in order to classify the device according to the characteristic. This allows for storing in a table look-up format, significant amounts of data about the characteristics of the device without requiring large amounts of memory on the device, and substantially relieving the testing system of a requirement for memory resources.
摘要翻译： PCT No.PCT / US97 / 18204 Sec。 371日期：1997年11月17日 102（e）日期1997年11月17日PCT 1997年10月8日PCT公布。公开号WO99 / 18531 日期1999年04月15日基于在器件中提供存储器单元的测试列的制造集成电路的方法。测试列中的单元格由标识设备主阵列中的行的地址的一部分来选择。执行测试以确定设备的特性，并将该测试的结果映射到标识阵列中的一行的地址部分。这产生了指示测试结果的设备的特征代码地址。启用对设备的测试列的访问，并响应于测试列上的存储单元中的特征代码地址写入一个位。在制造期间，读取测试柱以便根据特性对装置进行分类。这允许以表查找格式存储关于设备的特性的大量数据，而不需要设备上的大量存储器，并且基本上减轻了测试系统对存储器资源的需求。

5. 发明申请

US20130285737A1 Charge Pump System 有权
标题翻译：电荷泵系统
公开(公告)号：US20130285737A1
公开(公告)日：2013-10-31
申请号：US13460112
申请日：2012-04-30
申请人： Yung Feng Lin , Chun-Jen Huang , Tzeng-Huei Shiau , Chun-Hsiung Hung , Caiyun Wu , Qifang Wang
发明人： Yung Feng Lin , Chun-Jen Huang , Tzeng-Huei Shiau , Chun-Hsiung Hung , Caiyun Wu , Qifang Wang
IPC分类号： G05F3/02
CPC分类号： H02M3/07
摘要： In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.
摘要翻译：在一个方面，第一电荷泵具有串联布置的电荷泵级。相邻级之间的阶段节点由第二电荷泵泵送。在另一方面，电荷泵级的定时由命令时钟信号控制。命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

6. 发明授权

US09214859B2 Charge pump system 有权
标题翻译：电荷泵系统
公开(公告)号：US09214859B2
公开(公告)日：2015-12-15
申请号：US13460112
申请日：2012-04-30
申请人： Yung Feng Lin , Chun-Jen Huang , Tzeng-Huei Shiau , Chun-Hsiung Hung , Caiyun Wu , Qifang Wang
发明人： Yung Feng Lin , Chun-Jen Huang , Tzeng-Huei Shiau , Chun-Hsiung Hung , Caiyun Wu , Qifang Wang
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.
摘要翻译：在一个方面，第一电荷泵具有串联布置的电荷泵级。相邻级之间的阶段节点由第二电荷泵泵送。在另一方面，电荷泵级的定时由命令时钟信号控制。命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。

7. 发明授权

US06573780B2 Four-phase charge pump with lower peak current 有权
标题翻译：具有较低峰值电流的四相电荷泵
公开(公告)号：US06573780B2
公开(公告)日：2003-06-03
申请号：US09355654
申请日：1999-08-02
申请人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/075
摘要： A four-phase charge pump circuit suitable for use on integrated circuits, such as flash memory devices, includes circuitry that drives charge pump nodes in two components separated by a time delay. The two components can be triggered by edges from the clocks that control the timing of the charge pump. Driving the charge pump nodes in two components separated by a delay decreases the peak current of the charge pump and improves noise characteristics of a voltage supply or ground line connected to the charge pump.
摘要翻译：适用于集成电路（例如闪存器件）的四相电荷泵电路包括驱动由时间延迟分开的两个部件中的电荷泵节点的电路。这两个组件可以由控制电荷泵定时的时钟边沿触发。驱动由延迟分开的两个部件中的电荷泵节点会降低电荷泵的峰值电流，并改善连接到电荷泵的电源或接地线的噪声特性。

8. 发明授权

US6100557A Triple well charge pump 失效
标题翻译：三重充电泵
公开(公告)号：US6100557A
公开(公告)日：2000-08-08
申请号：US849561
申请日：1997-05-12
申请人： Chun-Hsiung Hung , Ray-Lin Wan , Yao-Wu Cheng
发明人： Chun-Hsiung Hung , Ray-Lin Wan , Yao-Wu Cheng
IPC分类号： H01L27/02 , H02M3/07 , H01L29/72
CPC分类号： H01L27/0222 , H02M3/073
摘要： An improved charge pump design is disclosed. This charge pump comprises at least one pumping transistor having a triple well arrangement. This triple pump transistor has a source and a drain region of a first conductive type formed on a first well having an opposite conductive type. A second well having the first conductive type is formed outside of the first well. The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region. Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage reduction, singly and in combination, allow the charge pump to operate more efficiently.
摘要翻译： PCT No.PCT / US96 / 16317 Sec。 371日期：1997年5月12日 102（e）日期1997年5月12日PCT提交1996年10月10日PCT公布。公开号WO98 / 16010 PCT 日期：1998年4月16日公开了改进的电荷泵设计。该电荷泵包括具有三阱布置的至少一个泵浦晶体管。该三重泵晶体管具有形成在具有相反导电类型的第一阱上的第一导电类型的源区和漏区。具有第一导电类型的第二阱形成在第一阱的外部。源区，第一阱和第二阱被设定为基本上相同的电位。该结构的一个方面是第一阱与漏极区形成半导体二极管。这种布置的另一方面是晶体管的体效减小。身体效应的降低降低了晶体管的阈值电压。发现上述二极管和阈值电压降低，单独并且组合地允许电荷泵更有效地操作。

9. 发明授权

US5875152A Address transition detection circuit for a semiconductor memory capable of detecting narrowly spaced address changes 失效
标题翻译：用于能够检测窄间隔地址变化的半导体存储器的地址转换检测电路
公开(公告)号：US5875152A
公开(公告)日：1999-02-23
申请号：US751513
申请日：1996-11-15
申请人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
发明人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18 , H03K5/1534 , G11C8/00 , H03K5/22
CPC分类号： H03K5/1534 , G11C7/22 , G11C8/18
摘要： The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input. The second circuit responsive to the change signal at the input generates an initialize command at the output. The circuit provides a second state at the output of the first circuit, for all including the last received in a series of change signals. This assures that all address transitions have been detected before a memory access is allowed.
摘要翻译：本发明提供一种新的（ATD）地址转换检测电路，用于具有任意数量的地址线的地址总线。公开了一种包括第一和第二电路和间隔定时器的ATD电路。第一电路具有第一和第二输入和输出。第一电路在第一输入端接收对应于地址总线的一个或多个地址中的转变的改变信号。作为响应，第一电路的输出从初始第一状态转变到第二状态。第一电路还响应于第二输入端的复位命令将输出返回到第一状态。间隔定时器具有耦合到第一电路的第二输入和输入的输出。响应于输入的初始化命令的间隔定时器启动定时间隔，并且在定时间隔之后在输出端产生复位命令。第二电路具有耦合到间隔定时器和输入的输入的输出。响应于输入端的变化信号的第二电路在输出端产生初始化命令。该电路在第一电路的输出处提供第二状态，包括在一系列变化信号中最后接收的信号。这确保在允许存储器访问之前已经检测到所有地址转换。

10. 发明授权

US06219290B1 Memory cell sense amplifier 有权
标题翻译：存储单元读出放大器
公开(公告)号：US06219290B1
公开(公告)日：2001-04-17
申请号：US09172274
申请日：1998-10-14
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
IPC分类号： G11C702
CPC分类号： G11C7/062 , G11C7/067 , G11C7/12 , G11C16/28
摘要： A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.
摘要翻译：描述了用于感测最小化读取时间的存储单元的逻辑状态的感测电路，其包括对应于阵列电路路径的第一电路支路和对应于参考单元电路路径的第二电路支路。在预解码间隔期间的操作中，在第一电路路径中启用额外的负载和电流产生电路，使得感测电路比较器的感测输入所看到的电压被驱动为基本上等于参考信号的电压，如由参考单元电路路径建立在感测电路比较器的参考输入端上。一旦解码了地址，则禁用附加负载电路，以便允许比较器的感测输入转换到代表存储在存储单元中的逻辑状态的电压。

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