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1. 发明授权

US08928094B2 Strained asymmetric source/drain 有权
标题翻译：应变不对称源/漏极
公开(公告)号：US08928094B2
公开(公告)日：2015-01-06
申请号：US12875834
申请日：2010-09-03
申请人： Chun-Fai Cheng , Ka-Hing Fung , Shyh-Wei Wang , Chin-Te Su
发明人： Chun-Fai Cheng , Ka-Hing Fung , Shyh-Wei Wang , Chin-Te Su
IPC分类号： H01L29/78 , H01L21/265 , H01L21/266 , H01L21/285 , H01L21/8238 , H01L29/165 , H01L29/66
CPC分类号： H01L29/66545 , H01L21/26586 , H01L21/266 , H01L21/28525 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/6656 , H01L29/66659 , H01L29/7835 , H01L29/7848
摘要： The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.
摘要翻译：本公开提供半导体器件及其制造方法，其中半导体器件具有应变的不对称源极和漏极区域。制造半导体器件的方法包括提供衬底并在衬底上形成多晶硅叠层。掺杂剂以垂直于衬底的约10°至约25°的注入角度注入衬底中。邻近衬底上的多晶硅叠层形成间隔物。源极区和漏极区被蚀刻在衬底中。应变源极层和应变漏极层分别沉积在衬底中的蚀刻源极和漏极区域中，使得源极区域和漏极区域相对于多晶硅栅极叠层是不对称的。多晶硅堆叠从衬底去除，并且使用去除多晶硅叠层的最后工艺形成高k金属栅极。

2. 发明申请

US20120056276A1 STRAINED ASYMMETRIC SOURCE/DRAIN 有权
标题翻译：应变不对称源/排水
公开(公告)号：US20120056276A1
公开(公告)日：2012-03-08
申请号：US12875834
申请日：2010-09-03
申请人： Chun-Fai Cheng , Ka-Hing Fung , Shyh-Wei Wang , Chin-Te Su
发明人： Chun-Fai Cheng , Ka-Hing Fung , Shyh-Wei Wang , Chin-Te Su
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/26586 , H01L21/266 , H01L21/28525 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/6656 , H01L29/66659 , H01L29/7835 , H01L29/7848
摘要： The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.
摘要翻译：本公开提供半导体器件及其制造方法，其中半导体器件具有应变的不对称源极和漏极区域。制造半导体器件的方法包括提供衬底并在衬底上形成多晶硅叠层。掺杂剂以垂直于衬底的约10°至约25°的注入角度注入衬底中。邻近衬底上的多晶硅叠层形成间隔物。源极区和漏极区被蚀刻在衬底中。应变源极层和应变漏极层分别沉积在衬底中的蚀刻源极和漏极区域中，使得源极区域和漏极区域相对于多晶硅栅极叠层是不对称的。多晶硅堆叠从衬底去除，并且使用去除多晶硅叠层的最后工艺形成高k金属栅极。

3. 发明授权

US08362573B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08362573B2
公开(公告)日：2013-01-29
申请号：US12787966
申请日：2010-05-26
申请人： Chung-Cheng Wu , Ali Keshavarzi , Ka Hing Fung , Ta-Pen Guo , Jiann-Tyng Tzeng , Yen-Ming Chen , Shyue-Shyh Lin , Shyh-Wei Wang , Sheng-Jier Yang , Hsiang-Jen Tseng , David B. Scott , Min Cao
发明人： Chung-Cheng Wu , Ali Keshavarzi , Ka Hing Fung , Ta-Pen Guo , Jiann-Tyng Tzeng , Yen-Ming Chen , Shyue-Shyh Lin , Shyh-Wei Wang , Sheng-Jier Yang , Hsiang-Jen Tseng , David B. Scott , Min Cao
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L27/092 , H01L29/7848 , H01L2224/16225
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域间隔开。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属层与第一源区电耦合。第一金属层和第一扩散区域与第一距离重叠。第二金属层与第一漏极区域和第二漏极区域电耦合。第二金属层和第一扩散区域与第二距离重叠。第一距离大于第二距离。

4. 发明申请

US20130277750A1 Semiconductor Device and Method for Forming Same 有权
公开(公告)号：US20130277750A1
公开(公告)日：2013-10-24
申请号：US13451261
申请日：2012-04-19
申请人： Jui-Yao Lai , Chun-Yi Lee , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jui-Yao Lai , Chun-Yi Lee , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L27/06 , H01L27/08
CPC分类号： H01L28/24 , H01L21/823842 , H01L23/5228 , H01L27/0629 , H01L27/0802 , H01L28/20 , H01L29/0649 , H01L29/0847 , H01L2924/0002 , H01L2924/00
摘要： A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

5. 发明授权

US08404544B1 Fabrication methods of integrated semiconductor structure 有权
标题翻译：集成半导体结构的制作方法
公开(公告)号：US08404544B1
公开(公告)日：2013-03-26
申请号：US13446769
申请日：2012-04-13
申请人： Jin-Mu Yin , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jin-Mu Yin , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/518 , H01L29/66545 , H01L29/66553 , H01L29/78
摘要： A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first gate stack, a second gate stack, and a third gate stack are formed over the substrate in the first region, the second region, and the third region, respectively. The first gate stack, the second gate stack, and the third gate stack comprise a sacrificial layer over a first dielectric layer. The first gate stack and the second gate stack are removed and a second dielectric layer is formed in the first region and the second region. The portion of second dielectric layer in the first region is transformed into a third dielectric layer by a treatment.
摘要翻译：一种用于制造集成电路器件的方法包括提供具有第一区域，第二区域和第三区域的衬底。分别在第一区域，第二区域和第三区域中的衬底上形成第一栅极堆叠，第二栅极堆叠和第三栅极堆叠。第一栅极堆叠，第二栅极堆叠和第三栅极堆叠包括在第一介电层上的牺牲层。去除第一栅极堆叠和第二栅极堆叠，并且在第一区域和第二区域中形成第二电介质层。通过处理将第一区域中的第二电介质层的部分转变成第三电介质层。

6. 发明申请

US20100237441A1 Gated Diode with Non-Planar Source Region 有权
标题翻译：非平面源区门控二极管
公开(公告)号：US20100237441A1
公开(公告)日：2010-09-23
申请号：US12778912
申请日：2010-05-12
申请人： Da-Wen Lin , Ying-Shiou Lin , Shyh-Wei Wang , Li-Ping Huang , Ying-Keung Leung , Carlis H. Diaz
发明人： Da-Wen Lin , Ying-Shiou Lin , Shyh-Wei Wang , Li-Ping Huang , Ying-Keung Leung , Carlis H. Diaz
IPC分类号： H01L29/739
CPC分类号： H01L29/7391 , H01L29/0657 , H01L29/42312 , H01L29/66356
摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.
摘要翻译：门控二极管半导体器件或类似部件及其制造方法。该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且与源极和漏极相邻。源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。如果两者都存在，则源极和漏极可以是对称的或非对称的。这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

7. 发明授权

US06461897B2 Multichip module having a stacked chip arrangement 有权
标题翻译：具有堆叠芯片布置的多芯片模块
公开(公告)号：US06461897B2
公开(公告)日：2002-10-08
申请号：US09854486
申请日：2001-05-15
申请人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao
发明人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/01087 , H01L2924/00014 , H01L2924/00012
摘要： A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
摘要翻译：多芯片模块包括至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。半导体芯片以堆叠方式安装到基板上，其中上芯片以下述方式附接到下芯片的有源表面，使得上芯片的任何部分不影响下芯片的每个键合焊盘的垂直视线芯片以允许其引线接合。因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

8. 发明授权

US06359340B1 Multichip module having a stacked chip arrangement 有权
标题翻译：具有堆叠芯片布置的多芯片模块
公开(公告)号：US06359340B1
公开(公告)日：2002-03-19
申请号：US09628676
申请日：2000-07-28
申请人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao , Jian Wen Chen
发明人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao , Jian Wen Chen
IPC分类号： H05K706
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2924/01087 , H01L2924/10253 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A multichip module has at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. In some embodiments, the semiconductor chips may have a plurality of bonding pads along only two mutually perpendicular side edges thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
摘要翻译：多芯片模块具有至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。在一些实施例中，半导体芯片可以具有仅沿着其两个相互垂直的侧边缘的多个接合焊盘。半导体芯片以堆叠方式安装到基板上，其中上部芯片以下述方式附接到下部芯片的有源表面，即，上部芯片的任何部分不影响下部芯片的每个焊盘的垂直视线芯片以允许其引线接合。因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

9. 发明授权

US06221697B1 Chip scale package and manufacturing method thereof 有权
标题翻译：芯片尺寸封装及其制造方法
公开(公告)号：US06221697B1
公开(公告)日：2001-04-24
申请号：US09475232
申请日：1999-12-30
申请人： Ching-Huei Su , Chih-Chang Yang , Shyh-Wei Wang , Chih-Sien Yeh
发明人： Ching-Huei Su , Chih-Chang Yang , Shyh-Wei Wang , Chih-Sien Yeh
IPC分类号： H01L2144
CPC分类号： H01L24/50 , H01L23/3114 , H01L2924/01005 , H01L2924/01027 , H01L2924/01082
摘要： A chip scale package mainly comprises two elastomer pads respectively interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively situated on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein bonding pads formed on the semiconductor chip are exposed from the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball. The chip scale package is electrically connected to outside through the solder balls. The slot of the substrate and the periphery of the semiconductor chip are sealed by an integrally formed package body. The present invention is characterized in that the encapsulation process of the chip scale package is carried out by a single step of dispensing and curing, so as to increase UPH (unit per hour) thereby shortening encapsulation cycle time. Moreover, the occurrence of flash on the substrate surface around the slot during encapsulation can be reduced, thereby assuring the solder joint reliability of the solder pads.
摘要翻译：芯片级封装主要包括分别介于基板和半导体芯片之间的两个弹性体垫。每个弹性体垫片分别位于中心地限定在基底中的狭槽的侧面上，并且保持与狭槽的预定距离。半导体芯片通过两个弹性体垫连接到基板的上表面上，其中形成在半导体芯片上的接合焊盘从基板的槽露出。基板的上表面设置有多个焊盘和引线。每个引线的一端电连接到相应的焊盘，另一端电连接到半导体芯片的相应的焊盘。衬底具有与焊料焊盘相对形成的多个通孔，使得每个焊盘具有露出在用于安装焊球的通孔内的部分。芯片级封装通过焊球与外部电连接。衬底的槽和半导体芯片的周边由整体形成的封装体密封。本发明的特征在于，通过单次分配和固化步骤进行芯片级封装的封装工艺，从而增加UPH（每小时单位），从而缩短封装周期时间。此外，可以减少在封装期间围绕槽的衬底表面上的闪光的发生，从而确保焊盘的焊点可靠性。

10. 发明授权

US08518780B1 Fabrication methods of integrated semiconductor structure 有权
标题翻译：集成半导体结构的制作方法
公开(公告)号：US08518780B1
公开(公告)日：2013-08-27
申请号：US13446852
申请日：2012-04-13
申请人： Jin-Mu Yin , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jin-Mu Yin , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L21/8232
CPC分类号： H01L21/823462 , H01L21/823857
摘要： A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first dielectric layer is formed in the first region of the substrate. A second dielectric layer is formed in the second region and the third region. A sacrificial layer is formed over the first dielectric layer and the second dielectric layer. The sacrificial layer, the first dielectric layer, and the second dielectric layer are patterned to form a first gate stack, a second gate stack, and a third gate stack. An interlayer dielectric (ILD) layer is formed in between the first gate stack, the second gate stack, and the third gate stack. The second gate stack is removed to form an opening adjacent to the ILD layer and a third dielectric layer is formed in the opening.
摘要翻译：一种用于制造集成电路器件的方法包括提供具有第一区域，第二区域和第三区域的衬底。第一电介质层形成在衬底的第一区域中。第二介电层形成在第二区域和第三区域中。牺牲层形成在第一电介质层和第二电介质层上。将牺牲层，第一介电层和第二介电层图案化以形成第一栅极堆叠，第二栅极堆叠和第三栅极堆叠。在第一栅极堆叠，第二栅极堆叠和第三栅极堆叠之间形成层间电介质层（ILD）层。去除第二栅极堆叠以形成与ILD层相邻的开口，并且在开口中形成第三电介质层。

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