专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06221697B1 Chip scale package and manufacturing method thereof 有权
标题翻译：芯片尺寸封装及其制造方法
公开(公告)号：US06221697B1
公开(公告)日：2001-04-24
申请号：US09475232
申请日：1999-12-30
申请人： Ching-Huei Su , Chih-Chang Yang , Shyh-Wei Wang , Chih-Sien Yeh
发明人： Ching-Huei Su , Chih-Chang Yang , Shyh-Wei Wang , Chih-Sien Yeh
IPC分类号： H01L2144
CPC分类号： H01L24/50 , H01L23/3114 , H01L2924/01005 , H01L2924/01027 , H01L2924/01082
摘要： A chip scale package mainly comprises two elastomer pads respectively interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively situated on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein bonding pads formed on the semiconductor chip are exposed from the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball. The chip scale package is electrically connected to outside through the solder balls. The slot of the substrate and the periphery of the semiconductor chip are sealed by an integrally formed package body. The present invention is characterized in that the encapsulation process of the chip scale package is carried out by a single step of dispensing and curing, so as to increase UPH (unit per hour) thereby shortening encapsulation cycle time. Moreover, the occurrence of flash on the substrate surface around the slot during encapsulation can be reduced, thereby assuring the solder joint reliability of the solder pads.
摘要翻译：芯片级封装主要包括分别介于基板和半导体芯片之间的两个弹性体垫。每个弹性体垫片分别位于中心地限定在基底中的狭槽的侧面上，并且保持与狭槽的预定距离。半导体芯片通过两个弹性体垫连接到基板的上表面上，其中形成在半导体芯片上的接合焊盘从基板的槽露出。基板的上表面设置有多个焊盘和引线。每个引线的一端电连接到相应的焊盘，另一端电连接到半导体芯片的相应的焊盘。衬底具有与焊料焊盘相对形成的多个通孔，使得每个焊盘具有露出在用于安装焊球的通孔内的部分。芯片级封装通过焊球与外部电连接。衬底的槽和半导体芯片的周边由整体形成的封装体密封。本发明的特征在于，通过单次分配和固化步骤进行芯片级封装的封装工艺，从而增加UPH（每小时单位），从而缩短封装周期时间。此外，可以减少在封装期间围绕槽的衬底表面上的闪光的发生，从而确保焊盘的焊点可靠性。

IPRDB

热门服务

关于我们

友情链接

联系方式