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1. 发明授权

US08369162B2 Input-output line sense amplifier having adjustable output drive capability 有权
公开(公告)号：US08369162B2
公开(公告)日：2013-02-05
申请号：US13316285
申请日：2011-12-09
申请人： Kang Yong Kim , Chulmin Jung
发明人： Kang Yong Kim , Chulmin Jung
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/1096 , G11C7/00 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C11/4091 , G11C11/4097 , G11C13/004 , H03F3/16
摘要： An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

2. 发明授权

US08203894B2 Current cancellation for non-volatile memory 有权
标题翻译：当前取消非易失性存储器
公开(公告)号：US08203894B2
公开(公告)日：2012-06-19
申请号：US13081170
申请日：2011-04-06
申请人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
发明人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
IPC分类号： G11C7/22
CPC分类号： G11C11/1673
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

3. 发明授权

US08045361B2 Non-volatile memory cell with complementary resistive memory elements 有权
标题翻译：具有互补电阻存储元件的非易失性存储单元
公开(公告)号：US08045361B2
公开(公告)日：2011-10-25
申请号：US12501140
申请日：2009-07-10
申请人： Hyung-Kyu Lee , YoungPil Kim , Chulmin Jung
发明人： Hyung-Kyu Lee , YoungPil Kim , Chulmin Jung
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C2013/0042 , G11C2013/0078 , G11C2013/0088 , G11C2213/79
摘要： A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current in a selected direction through the memory cell.
摘要翻译：非易失性存储单元和向其写入数据的方法。根据一些实施例，存储器单元包括被配置为同时存储互补的编程电阻状态的第一和第二电阻性存储元件（RME）。第一RME被编程为第一电阻状态，并且通过在所选择的方向上通过存储器单元施加公共写入电流，将第二RME同时编程为第二电阻状态。

4. 发明申请

US20110007597A1 Semiconductor Control Line Address Decoding Circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US20110007597A1
公开(公告)日：2011-01-13
申请号：US12502219
申请日：2009-07-13
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

5. 发明申请

US20100302849A1 NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE 有权
标题翻译：具有集成位线电容的NAND闪存
公开(公告)号：US20100302849A1
公开(公告)日：2010-12-02
申请号：US12474463
申请日：2009-05-29
申请人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
发明人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C11/005 , G11C16/26 , G11C2216/14
摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
摘要翻译：用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。在一些实施例中，易失性存储器单元是来自所述单元的行的动态随机存取存储器（DRAM）单元，其中每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元包括以NAND配置连接的闪存单元。

6. 发明申请

US20100019804A1 ARRAY SENSE AMPLIFIERS, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF OPERATION 有权
标题翻译：阵列感知放大器，包括其的存储器件和系统以及操作方法
公开(公告)号：US20100019804A1
公开(公告)日：2010-01-28
申请号：US12573750
申请日：2009-10-05
申请人： Chulmin Jung , Tae Kim
发明人： Chulmin Jung , Tae Kim
IPC分类号： H03F3/45
CPC分类号： G11C7/065 , G11C11/4091
摘要： A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.
摘要翻译：描述了具有减小的增益的放大器级的读出放大器。读出放大器包括第一输入/输出（“I / O”）节点和第二互补I / O节点。读出放大器包括两个放大器级，每个用于放大I / O节点之一上的信号。具有第一导电类型的第一放大器级将第一电压的I / O节点之一放大。具有第二导电类型的第二放大器级将第二电压放大到另一个I / O节点。读出放大器还包括耦合到第二放大器级的电阻电路，以减小第二放大器级的增益，从而降低相应I / O节点上的信号的放大率。

7. 发明申请

US20090316496A1 INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY 有权
标题翻译：具有可调输出驱动能力的输入输出线路感测放大器
公开(公告)号：US20090316496A1
公开(公告)日：2009-12-24
申请号：US12549200
申请日：2009-08-27
申请人： Kang Yong Kim , Chulmin Jung
发明人： Kang Yong Kim , Chulmin Jung
IPC分类号： G11C7/10 , G11C8/00 , G11C7/02
CPC分类号： G11C7/1096 , G11C7/00 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C11/4091 , G11C11/4097 , G11C13/004 , H03F3/16
摘要： An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.
摘要翻译：输入 - 输出线路读出放大器被配置为通过输入 - 输出信号线将输入数据信号驱动到输出驱动器电路，输入 - 输出线路读出放大器具有输出驱动级，其具有多个不同的可编程输出驱动能力，以定制读出放大器的输出驱动。

8. 发明授权

US07567465B2 Power saving sensing scheme for solid state memory 有权
标题翻译：固态存储器的省电感测方案
公开(公告)号：US07567465B2
公开(公告)日：2009-07-28
申请号：US11847559
申请日：2007-08-30
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C7/103 , G11C8/18
摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.
摘要翻译：公开了诸如涉及固态存储器件的方法和装置。一种这样的方法包括选择存储器阵列中的多个存储器单元。确定存储在所选择的多个存储单元中的多个数据位的状态。在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。顺序提供多个数据位作为输出。在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。

9. 发明申请

US20060126405A1 Apparatus with equalizing voltage generation circuit and methods of use 有权
标题翻译：具有均衡电压产生电路和使用方法的装置
公开(公告)号：US20060126405A1
公开(公告)日：2006-06-15
申请号：US11347961
申请日：2006-02-06
申请人： Chulmin Jung
发明人： Chulmin Jung
IPC分类号： G11C7/06
CPC分类号： G11C11/4094
摘要： A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced by a feedback and control loop of the equalization voltage generator. The feedback and control loop includes a reference generator circuit to produce a stable, internal reference signal that is clamped at a maximum reference voltage. A comparator of the feedback and control loop compares the internal reference signal with a second voltage, which is proportional to the first voltage. The comparator causes the oscillator to turn on when the second voltage is lower than the reference voltage, and causes the oscillator to turn off when the second voltage is higher than the reference voltage.
摘要翻译：存储器件包括均衡电压发生器。均衡电压发生器包括振荡器和电荷泵以产生第一电压，其可以用作互补数字线对的均衡电压。振荡器由均衡电压发生器的反馈和控制回路产生的振荡器控制信号控制。反馈和控制回路包括参考发生器电路，以产生稳定的内部参考信号，其被钳位在最大参考电压。反馈和控制环路的比较器将内部参考信号与第一电压成比例的第二电压进行比较。当第二电压低于参考电压时，比较器使振荡器导通，并且当第二电压高于参考电压时使振荡器关断。

10. 发明申请

US20130044550A1 Memory Array Having Word Lines with Folded Architecture 有权
标题翻译：具有折叠架构的字线的内存阵列
公开(公告)号：US20130044550A1
公开(公告)日：2013-02-21
申请号：US13213019
申请日：2011-08-18
申请人： Chulmin Jung , Myron Buer
发明人： Chulmin Jung , Myron Buer
IPC分类号： G11C7/10
CPC分类号： G11C7/1012 , G11C5/025 , G11C8/14 , G11C11/4085 , G11C11/4087
摘要： According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes a multiplexer for coupling one memory cell in a selected group of columns to at least one of the plurality of sense amps, thereby achieving a reduced sense amp-to-column ratio. The memory array arrangement further includes a plurality of I/O buffers each corresponding to the at least one of the plurality of sense amps. The memory array arrangement thereby results in the plurality of word lines having reduced resistive and capacitive loading.
摘要翻译：根据示例性实施例，存储器阵列布置包括多个字线，其中多条字线中的至少两条字线是同时有效的字线。多个字线中的每一个驱动至少一组列。存储器阵列布置还包括多路复用器，用于将所选择的列组中的一个存储器单元耦合到多个感测放大器中的至少一个，从而实现减小的读出放大比率。存储器阵列布置还包括多个I / O缓冲器，每个I / O缓冲器对应于多个感测放大器中的至少一个。因此，存储器阵列布置导致多个字线具有降低的电阻和电容负载。

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