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1. 发明授权

US06216222B1 Handling exceptions in a pipelined data processing apparatus 失效
标题翻译：处理流水线数据处理设备中的异常
公开(公告)号：US06216222B1
公开(公告)日：2001-04-10
申请号：US09078595
申请日：1998-05-14
申请人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , Matthew Paul Elwood
发明人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , Matthew Paul Elwood
IPC分类号： G06F9302
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3867
摘要： A data processing apparatus and method is provided, the apparatus comprising an execution unit having a plurality of pipelined stages for executing instructions, such that a maximum of ‘n’ instructions can be being executed simultaneously within the execution unit. Further, a set of at least ‘n’ logical exception registers are provided, each exception register being capable of storing a number of exception attributes associated with an instruction for which an exception has been detected during execution by the execution unit. In the event of an exception being detected during execution of a first instruction, the execution unit is arranged to: (i) store in a first of said exception registers said exception attributes associated with said first instruction; and (ii) to continue executing any remaining instructions already in the pipelined stages at the time the exception was detected. The execution unit is further arranged to store in said exception registers the exception attributes associated with any of the remaining instructions for which an exception is detected during execution, whereby the exception attributes stored in the exception registers can be provided to an exception processing tool for use in recovering from any exceptions occurring during processing of said first instruction and said remaining instructions. By this approach, when the exception processing tool is invoked, then it can deal with any exceptions arising from the instructions executed by the pipeline, and the data processing apparatus can then continue with the next instruction, without the need to re-execute any of the instructions that were in the pipeline at the time the first exception was detected.
摘要翻译：提供了一种数据处理装置和方法，该装置包括具有多个流水线级的执行单元，用于执行指令，使得在执行单元内可以同时执行“n”个指令的最大值，此外，提供了至少“n”个逻辑异常寄存器，每个异常寄存器能够存储与由执行单元执行期间检测到异常的指令相关联的多个异常属性。在执行第一指令期间检测到异常的情况下，执行单元被配置为：（i）在所述异常寄存器的第一个中存储与所述第一指令相关联的异常属性; 和（ii）在检测到异常时继续执行已经在流水线阶段中的任何剩余指令。所述执行单元还被布置为在所述异常寄存器中存储与执行期间检测到异常的任何剩余指令相关联的异常属性，从而可以将异常寄存器中存储的异常属性提供给用于使用的异常处理工具在从所述第一指令和所述剩余指令的处理期间发生的任何异常中恢复。通过这种方法，当调用异常处理工具时，它可以处理由流水线执行的指令引起的任何异常，然后数据处理设备可以继续下一个指令，而不需要重新执行任何在检测到第一个异常时正在流水线中的指令。

2. 发明授权

US06360189B1 Data processing apparatus and method for performing multiply-accumulate operations 有权
标题翻译：用于进行多重累加操作的数据处理装置和方法
公开(公告)号：US06360189B1
公开(公告)日：2002-03-19
申请号：US09144264
申请日：1998-08-31
申请人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny
发明人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny
IPC分类号： G06F738
CPC分类号： G06F9/30098 , G06F7/483 , G06F7/49957 , G06F7/5443 , G06F9/30087 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/345 , G06F9/3455 , G06F9/3838 , G06F9/3877
摘要： A data processing apparatus and method is provided for performing a multiply-accumulate operation A+(B*C) in response to a single instruction identifying said multiply-accumulate operation. The data processing operation comprises a multiplier for multiplying values B and C to generate an unrounded multiplication result, the multiplier further being arranged to generate first data required for rounding determination, and an adder for adding the unrounded multiplication result to a value A to generate an unrounded multiply-accumulate result, the adder further being arranged to generate second data required for rounding determination. Determination logic is then provided for using the first and second data to determine one or more rounding values required to produce a final multiply-accumulate result equivalent to the execution of a separate multiply instruction incorporating rounding, followed by a separate add instruction incorporating rounding. Rounding logic is then arranged to apply the one or more rounding values to generate the final multiply-accumulate result. By this approach, dedicated multiply-accumulate logic can be provided to enable fast execution of a multiply-accumulate instruction, whilst producing a result which is compliant with the IEEE 754-1985 standard.
摘要翻译：提供了一种数据处理装置和方法，用于响应于识别所述乘法累积操作的单个指令执行乘法累加运算A +（B * C）。该数据处理操作包括用于将值B和C相乘以产生未被四舍五入的乘法结果的乘法器，该乘法器进一步被布置为产生舍入确定所需的第一数据，以及用于将未被包围的乘法结果与值A相加的加法器，未包围的乘法累积结果，所述加法器还被布置成产生舍入确定所需的第二数据。然后提供确定逻辑以使用第一和第二数据来确定产生与执行包含舍入的单独乘法指令相等的最终乘法累积结果所需的一个或多个舍入值，随后是包含舍入的单独加法指令。然后将舍入逻辑布置成应用一个或多个舍入值以产生最终的乘法累加结果。通过该方法，可以提供专用的乘法累加逻辑，以便能够快速执行乘法累加指令，同时产生一个结果，符合IEEE 754-1985标准。

3. 发明授权

US06282634B1 Apparatus and method for processing data having a mixed vector/scalar register file 失效
标题翻译：用于处理具有混合向量/标量寄存器文件的数据的装置和方法
公开(公告)号：US06282634B1
公开(公告)日：2001-08-28
申请号：US09084304
申请日：1998-05-27
申请人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , David James Seal
发明人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , David James Seal
IPC分类号： G06F930
CPC分类号： G06F9/30098 , G06F7/483 , G06F7/49957 , G06F7/5443 , G06F9/30087 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/345 , G06F9/3455 , G06F9/3838 , G06F9/3877
摘要： A floating point unit is provided with a register bank comprising 32 registers that may be used as either vector registers of scalar registers. A data processing instruction includes at least one register specifying field pointing to a register containing a data value to be used in that operation. An increase in the instruction bit space available to encode more opcodes or to allow for more registers is provided by encoding whether a register is to be treated as a vector or a scalar within the register field itself. Further, the register field for one register of the instruction may encode whether another register is a vector or a scalar. The registers can be initially accessed using the values within the register fields of the instruction independently of the opcode allowing for easier decode.
摘要翻译：浮点单元设有一个寄存器组，包括32个寄存器，可用作标量寄存器的向量寄存器。数据处理指令包括指向包含要在该操作中使用的数据值的寄存器的至少一个寄存器指定字段。通过编码寄存器是否被视为寄存器字段本身中的向量或标量，可以提供可用于编码更多操作码或允许更多寄存器的指令位空间的增加。此外，指令的一个寄存器的寄存器字段可以编码另一寄存器是矢量还是标量。可以使用独立于操作码的指令的寄存器字段内的值来初始访问寄存器，从而更容易解码。

4. 发明授权

US06189094B1 Recirculating register file 失效
标题翻译：循环寄存器文件
公开(公告)号：US06189094B1
公开(公告)日：2001-02-13
申请号：US09085752
申请日：1998-05-27
申请人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , David James Seal
发明人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , David James Seal
IPC分类号： G06F1578
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3867
摘要： A floating point unit having a register bank containing a plurality of registers supports vector operations that execute a specified operation a plurality of times upon a sequence of data values form different registers. The register bank is divided into subsets and with the sequence of registers used in a vector operation wrapping within a subset. The subsets comprise disjoint, contiguous ranges of register numbers. The wrapping within ranges allows compact code and efficient to be provided for performing DSP operations, such as FIR filtering and matrix transformations.
摘要翻译：具有包含多个寄存器的寄存器组的浮点单元支持在数据值序列形成不同寄存器时多次执行指定操作的向量操作。寄存器组被划分为子集以及在子集中的矢量操作中使用的寄存器序列。子集包括不相交的寄存器编号的连续范围。范围内的包装允许紧凑的代码和有效的提供用于执行DSP操作，如FIR滤波和矩阵转换。

5. 发明授权

US6148314A Round increment in an adder circuit 有权
标题翻译：加法器电路中的加法
公开(公告)号：US6148314A
公开(公告)日：2000-11-14
申请号：US143614
申请日：1998-08-28
申请人： David Terrence Matheny , David Vivian Jaggar , David James Seal
发明人： David Terrence Matheny , David Vivian Jaggar , David James Seal
IPC分类号： G06F7/485 , G06F7/50 , G06F7/544
CPC分类号： G06F7/485 , G06F7/5443 , G06F7/49947
摘要： A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to subsequent normalization by a normalizer 60 and rounding by an incrementer 64. If an operation is performed that is immediately followed by an addition operation using the result of the preceding operation, then the normalized but unrounded sum is fed back to the adder 16 together with an indication of its rounding requirement. This rounding requirement can be performed by the adder 16 in parallel with the execution of the following addition by using the carry-in bit of the adder 16 to apply any increment required to rounding of the preceding result.
摘要翻译：描述了执行附加操作的浮点单元。浮点单元内的加法器16接收第一输入和第二输入以产生和。该总和经归一化器60随后归一化，并由加法器64进行舍入。如果使用前一操作的结果紧接着进行加法运算的操作，则将归一化但未被包围的和反馈到加法器16以及其舍入要求的指示。该加法器16可以通过使用加法器16的进位位并行执行后续加法来执行舍入要求，以应用对前一结果进行舍入所需的任何增量。

6. 发明授权

US6115729A Floating point multiply-accumulate unit 有权
标题翻译：浮点乘积累积单位
公开(公告)号：US6115729A
公开(公告)日：2000-09-05
申请号：US136843
申请日：1998-08-20
申请人： David Terrence Matheny , David Vivian Jaggar
发明人： David Terrence Matheny , David Vivian Jaggar
IPC分类号： G06F7/487 , G06F7/485 , G06F7/52 , G06F7/527 , G06F7/544 , G06F7/38
CPC分类号： G06F7/5443 , G06F7/483
摘要： A floating point unit 10 provides a multiply-accumulate operation to determine a result B+(A*C). The multiplier 20 takes several processing cycles to determine the product (A*C). Whilst the multiplier 20 and its subsequent carry-save-adder 26 operate, an aligned value B' of the addend B is generated by an alignment-shifter 34. The aligned-addend B' may only partially overlap with the product (A*C) to which it is to be added using an adder 44. Any high-order-portion HOP of the aligned-addend B' that does not overlap with the product (A*C) must be subsequently concatenated with the output of the adder 44 that sums the product (A*C) with the overlapping portion of the aligned-addend B'. If the sum performed by the adder 44 generates a carry then it is an incremented version IHOP of the high-order-portion that should be concatenated with the output of the adder 44. This incremented-high-order-portion is generated by the adder 44 during otherwise idle processing cycles present due to the multiplier 20 operating over multiple cycles.
摘要翻译：浮点单元10提供乘积累运算以确定结果B +（A * C）。乘法器20需要几个处理周期来确定乘积（A * C）。虽然乘法器20及其随后的进位保存加法器26运行，加法器B的对准值B'由对准移位器34产生。对齐加法器B'可以仅部分地与产品重叠（A * C ），并且与乘积（A * C）不重叠的对齐加法器B'的任何高阶部分HOP必须随后与加法器44的输出连接将产品（A * C）与对齐加法器B'的重叠部分相加。如果由加法器44执行的和产生进位，则它是应该与加法器44的输出相连的高阶部分的递增版本IHOP。这个递增高阶部分由加法器在另外的空闲处理周期期间由于倍增器20在多个周期上操作而存在。

7. 发明授权

US06542916B1 Data processing apparatus and method for applying floating-point operations to first, second and third operands 有权
标题翻译：用于将浮点运算应用于第一，第二和第三操作数的数据处理装置和方法
公开(公告)号：US06542916B1
公开(公告)日：2003-04-01
申请号：US09362182
申请日：1999-07-28
申请人： Christopher Neal Hinds , David Vivian Jaggar , David James Seal
发明人： Christopher Neal Hinds , David Vivian Jaggar , David James Seal
IPC分类号： G06F738
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49947
摘要： A data processing apparatus and method is provided for applying a floating-point multiply-accumulate operation to first, second and third operands. The apparatus comprises a multiplier for multiplying the second and third operands and applying rounding to produce a rounded multiplication result, and an adder for adding the rounded multiplication result to the first operand to generate a final result and for applying rounding to generate a rounded final result. Further, control logic is provided which is responsive to a first single instruction to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the first operand. In preferred embodiments, the control logic is also responsive to a further single instruction to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the negated first operand. By this approach, multiply-accumulate logic can be arranged to provide fast execution of a first single instruction to generate a result equivalent to the subtraction of the rounded multiplication result from the first operand, or a second single instruction to generate a result equivalent to the subtraction of the rounded multiplication result from the negated first operand, whilst producing results which are compliant with the IEEE 754-1985 standard.
摘要翻译：提供了一种数据处理装置和方法，用于将浮点乘法累加运算应用于第一，第二和第三操作数。该装置包括用于乘以第二和第三操作数并应用舍入以产生舍入乘法结果的乘法器，以及用于将舍入乘法结果与第一操作数相加以产生最终结果并用于应用舍入以产生舍入的最终结果的加法器。此外，提供控制逻辑，其响应于第一单个指令来控制乘法器和加法器，以使由加法器产生的舍入最终结果等效于从第一操作数减去舍入乘法结果。在优选实施例中，控制逻辑还响应于另一单个指令来控制乘法器和加法器，以使由加法器产生的舍入最终结果等效于从否定的第一操作数的舍入乘法结果的相减。这样方法，乘法累加逻辑可以被布置为提供快速执行第一单个指令以产生等效于从第一操作数减去舍入乘法结果的结果，或者产生第二单个指令以产生等效于相减来自否定的第一操作数的舍入乘积，同时产生符合IEEE 754-1985标准的结果。

8. 发明授权

US06321329B1 Executing debug instructions 有权
标题翻译：执行调试指令
公开(公告)号：US06321329B1
公开(公告)日：2001-11-20
申请号：US09314025
申请日：1999-05-19
申请人： David Vivian Jaggar , William Adam Hohl
发明人： David Vivian Jaggar , William Adam Hohl
IPC分类号： G06F930
CPC分类号： G06F11/3632 , G06F11/3648
摘要： Apparatus for processing data is provided, said apparatus comprising: a main processor 4 driven by a main processor clock signal clk at a main processor clock frequency; debug logic 6, 12 at least a portion 12 of which is driven by a debug clock signal tck at a debug clock frequency, said debug clock frequency being different to said main processor clock frequency and said main processor clock signal clk being asynchronous with said debug clock signal tck; and an instruction transfer register ITR into which a data processing instruction may be transferred by said debug logic 12 and from which said data processing instruction may be read by said main processor 4; wherein when switched from a normal mode to a debug mode said main processor 4 continues to be driven by said main processor clock signal clk executing no-operation instructions until a data processing instruction is present within said instruction transfer register ITR and said debug logic 12 triggers said main processor to read and execute said data processing instruction whilst still driven by said main processor clock signal clk. This arrangement allows debug instructions to be executed at full speed whilst avoiding the need to switch clock speeds and provide a synchronisation mechanism.
摘要翻译：提供用于处理数据的装置，所述装置包括：主处理器4，主处理器4以主处理器时钟频率由主处理器时钟信号clk驱动; 调试逻辑6,12，其中至少一部分12以调试时钟频率由调试时钟信号tck驱动，所述调试时钟频率与所述主处理器时钟频率不同，并且所述主处理器时钟信号clk与所述调试异步时钟信号tck; 以及指令传送寄存器ITR，数据处理指令可由所述调试逻辑12传送到其中，所述数据处理指令可由所述主处理器4读取; 其中当从正常模式切换到调试模式时，所述主处理器4继续由所述主处理器时钟信号clk驱动，执行无操作指令，直到在所述指令传送寄存器ITR中存在数据处理指令，并且所述调试逻辑12触发所述主处理器在仍然由所述主处理器时钟信号clk驱动的同时读取和执行所述数据处理指令。这种布置允许调试指令以全速执行，同时避免需要切换时钟速度并提供同步机制。

9. 发明授权

US5680599A Program counter save on reset system and method 失效
标题翻译：程序计数器保存在复位系统和方法上
公开(公告)号：US5680599A
公开(公告)日：1997-10-21
申请号：US585247
申请日：1995-12-22
申请人： David Vivian Jaggar
发明人： David Vivian Jaggar
IPC分类号： G06F1/24 , G06F11/14 , G06F11/28 , G06F9/46
CPC分类号： G06F11/1441
摘要： A data processing apparatus and method are described in which a reset function for recovering from a system crash is provided. Upon activation of a reset signal (nRESET), the contents of a program counter (R15pc) are saved within another register (R14svc) prior to the reinitialization of the system. The contents of the register saving the program counter value are preserved through the reset operation to provide information to a person seeking to debug the system as to where a particular problem requiring the reset signal to be initiated occurred within the instruction address sequence.
摘要翻译：描述了一种用于从系统崩溃中恢复的复位功能的数据处理装置和方法。激活复位信号（nRESET）后，程序计数器（R15pc）的内容将在系统重新初始化之前保存在另一个寄存器（R14svc）中。保存程序计数器值的寄存器的内容通过复位操作被保留，以向寻求调试系统的人提供信息，以便在指令地址序列内发生需要启动复位信号的特定问题。

10. 发明授权

US06247113B1 Coprocessor opcode division by data type 失效
标题翻译：协处理器操作码按数据类型划分
公开(公告)号：US06247113B1
公开(公告)日：2001-06-12
申请号：US09084386
申请日：1998-05-27
申请人： David Vivian Jaggar
发明人： David Vivian Jaggar
IPC分类号： G06F1500
CPC分类号： G06F9/30192 , G06F9/30098 , G06F9/30112 , G06F9/3877
摘要： A data processing system having a main processor and a coprocessor. The main processor responsds to coprocessor instructions within its instruction stream by issuing the coprocessor instructions upon a coprocessor bus and detecting if the coprocessor accepts them by returning an accept signal. The coprocessor instructions include a coprocessor number and the coprocessor checks this number to see if it matches its own number(s) to determine whether or not it should accept the coprocessor instruction. A data type field within the coprocessor number in the coprocessor instruction also serves to specify one of multiple data types to be used in the coprocessor operation; particular coprocessors can interpret this part of the coprocessor number to determine data type. If the coprocessor supports multiple data types, then it has multiple coprocessor numbers for which it will issue accept signals and then uses the data type field to control the data type used. If a coprocessor does not support a particular data type then it will not issue an accept signal for coprocessor instructions that specify that data type. The main processor can then use emulation code to provide support for that coprocessor instruction.
摘要翻译：一种具有主处理器和协处理器的数据处理系统。主处理器通过在协处理器总线上发出协处理器指令并检测协处理器是否通过返回接收信号来接受协处理器指令来响应其指令流中的协处理器指令。协处理器指令包括协处理器号，协处理器检查该号码以查看它是否匹配其自己的号码，以确定是否应该接受协处理器指令。协处理器指令中的协处理器号内的数据类型字段还用于指定在协处理器操作中要使用的多种数据类型之一; 特定的协处理器可以解释协处理器号码的这一部分来确定数据类型。如果协处理器支持多种数据类型，那么它有多个协处理器编号，它将发出接受信号，然后使用数据类型字段来控制所使用的数据类型。如果协处理器不支持特定数据类型，那么它不会发出指定该数据类型的协处理器指令的接受信号。然后，主处理器可以使用仿真代码来为该协处理器指令提供支持。

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