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1. 发明授权

US06216222B1 Handling exceptions in a pipelined data processing apparatus 失效
标题翻译：处理流水线数据处理设备中的异常
公开(公告)号：US06216222B1
公开(公告)日：2001-04-10
申请号：US09078595
申请日：1998-05-14
申请人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , Matthew Paul Elwood
发明人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , Matthew Paul Elwood
IPC分类号： G06F9302
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3867
摘要： A data processing apparatus and method is provided, the apparatus comprising an execution unit having a plurality of pipelined stages for executing instructions, such that a maximum of ‘n’ instructions can be being executed simultaneously within the execution unit. Further, a set of at least ‘n’ logical exception registers are provided, each exception register being capable of storing a number of exception attributes associated with an instruction for which an exception has been detected during execution by the execution unit. In the event of an exception being detected during execution of a first instruction, the execution unit is arranged to: (i) store in a first of said exception registers said exception attributes associated with said first instruction; and (ii) to continue executing any remaining instructions already in the pipelined stages at the time the exception was detected. The execution unit is further arranged to store in said exception registers the exception attributes associated with any of the remaining instructions for which an exception is detected during execution, whereby the exception attributes stored in the exception registers can be provided to an exception processing tool for use in recovering from any exceptions occurring during processing of said first instruction and said remaining instructions. By this approach, when the exception processing tool is invoked, then it can deal with any exceptions arising from the instructions executed by the pipeline, and the data processing apparatus can then continue with the next instruction, without the need to re-execute any of the instructions that were in the pipeline at the time the first exception was detected.
摘要翻译：提供了一种数据处理装置和方法，该装置包括具有多个流水线级的执行单元，用于执行指令，使得在执行单元内可以同时执行“n”个指令的最大值，此外，提供了至少“n”个逻辑异常寄存器，每个异常寄存器能够存储与由执行单元执行期间检测到异常的指令相关联的多个异常属性。在执行第一指令期间检测到异常的情况下，执行单元被配置为：（i）在所述异常寄存器的第一个中存储与所述第一指令相关联的异常属性; 和（ii）在检测到异常时继续执行已经在流水线阶段中的任何剩余指令。所述执行单元还被布置为在所述异常寄存器中存储与执行期间检测到异常的任何剩余指令相关联的异常属性，从而可以将异常寄存器中存储的异常属性提供给用于使用的异常处理工具在从所述第一指令和所述剩余指令的处理期间发生的任何异常中恢复。通过这种方法，当调用异常处理工具时，它可以处理由流水线执行的指令引起的任何异常，然后数据处理设备可以继续下一个指令，而不需要重新执行任何在检测到第一个异常时正在流水线中的指令。

2. 发明授权

US06360189B1 Data processing apparatus and method for performing multiply-accumulate operations 有权
标题翻译：用于进行多重累加操作的数据处理装置和方法
公开(公告)号：US06360189B1
公开(公告)日：2002-03-19
申请号：US09144264
申请日：1998-08-31
申请人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny
发明人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny
IPC分类号： G06F738
CPC分类号： G06F9/30098 , G06F7/483 , G06F7/49957 , G06F7/5443 , G06F9/30087 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/345 , G06F9/3455 , G06F9/3838 , G06F9/3877
摘要： A data processing apparatus and method is provided for performing a multiply-accumulate operation A+(B*C) in response to a single instruction identifying said multiply-accumulate operation. The data processing operation comprises a multiplier for multiplying values B and C to generate an unrounded multiplication result, the multiplier further being arranged to generate first data required for rounding determination, and an adder for adding the unrounded multiplication result to a value A to generate an unrounded multiply-accumulate result, the adder further being arranged to generate second data required for rounding determination. Determination logic is then provided for using the first and second data to determine one or more rounding values required to produce a final multiply-accumulate result equivalent to the execution of a separate multiply instruction incorporating rounding, followed by a separate add instruction incorporating rounding. Rounding logic is then arranged to apply the one or more rounding values to generate the final multiply-accumulate result. By this approach, dedicated multiply-accumulate logic can be provided to enable fast execution of a multiply-accumulate instruction, whilst producing a result which is compliant with the IEEE 754-1985 standard.
摘要翻译：提供了一种数据处理装置和方法，用于响应于识别所述乘法累积操作的单个指令执行乘法累加运算A +（B * C）。该数据处理操作包括用于将值B和C相乘以产生未被四舍五入的乘法结果的乘法器，该乘法器进一步被布置为产生舍入确定所需的第一数据，以及用于将未被包围的乘法结果与值A相加的加法器，未包围的乘法累积结果，所述加法器还被布置成产生舍入确定所需的第二数据。然后提供确定逻辑以使用第一和第二数据来确定产生与执行包含舍入的单独乘法指令相等的最终乘法累积结果所需的一个或多个舍入值，随后是包含舍入的单独加法指令。然后将舍入逻辑布置成应用一个或多个舍入值以产生最终的乘法累加结果。通过该方法，可以提供专用的乘法累加逻辑，以便能够快速执行乘法累加指令，同时产生一个结果，符合IEEE 754-1985标准。

3. 发明授权

US06282634B1 Apparatus and method for processing data having a mixed vector/scalar register file 失效
标题翻译：用于处理具有混合向量/标量寄存器文件的数据的装置和方法
公开(公告)号：US06282634B1
公开(公告)日：2001-08-28
申请号：US09084304
申请日：1998-05-27
申请人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , David James Seal
发明人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , David James Seal
IPC分类号： G06F930
CPC分类号： G06F9/30098 , G06F7/483 , G06F7/49957 , G06F7/5443 , G06F9/30087 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/345 , G06F9/3455 , G06F9/3838 , G06F9/3877
摘要： A floating point unit is provided with a register bank comprising 32 registers that may be used as either vector registers of scalar registers. A data processing instruction includes at least one register specifying field pointing to a register containing a data value to be used in that operation. An increase in the instruction bit space available to encode more opcodes or to allow for more registers is provided by encoding whether a register is to be treated as a vector or a scalar within the register field itself. Further, the register field for one register of the instruction may encode whether another register is a vector or a scalar. The registers can be initially accessed using the values within the register fields of the instruction independently of the opcode allowing for easier decode.
摘要翻译：浮点单元设有一个寄存器组，包括32个寄存器，可用作标量寄存器的向量寄存器。数据处理指令包括指向包含要在该操作中使用的数据值的寄存器的至少一个寄存器指定字段。通过编码寄存器是否被视为寄存器字段本身中的向量或标量，可以提供可用于编码更多操作码或允许更多寄存器的指令位空间的增加。此外，指令的一个寄存器的寄存器字段可以编码另一寄存器是矢量还是标量。可以使用独立于操作码的指令的寄存器字段内的值来初始访问寄存器，从而更容易解码。

4. 发明授权

US06189094B1 Recirculating register file 失效
标题翻译：循环寄存器文件
公开(公告)号：US06189094B1
公开(公告)日：2001-02-13
申请号：US09085752
申请日：1998-05-27
申请人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , David James Seal
发明人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , David James Seal
IPC分类号： G06F1578
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3867
摘要： A floating point unit having a register bank containing a plurality of registers supports vector operations that execute a specified operation a plurality of times upon a sequence of data values form different registers. The register bank is divided into subsets and with the sequence of registers used in a vector operation wrapping within a subset. The subsets comprise disjoint, contiguous ranges of register numbers. The wrapping within ranges allows compact code and efficient to be provided for performing DSP operations, such as FIR filtering and matrix transformations.
摘要翻译：具有包含多个寄存器的寄存器组的浮点单元支持在数据值序列形成不同寄存器时多次执行指定操作的向量操作。寄存器组被划分为子集以及在子集中的矢量操作中使用的寄存器序列。子集包括不相交的寄存器编号的连续范围。范围内的包装允许紧凑的代码和有效的提供用于执行DSP操作，如FIR滤波和矩阵转换。

5. 发明授权

US6115729A Floating point multiply-accumulate unit 有权
标题翻译：浮点乘积累积单位
公开(公告)号：US6115729A
公开(公告)日：2000-09-05
申请号：US136843
申请日：1998-08-20
申请人： David Terrence Matheny , David Vivian Jaggar
发明人： David Terrence Matheny , David Vivian Jaggar
IPC分类号： G06F7/487 , G06F7/485 , G06F7/52 , G06F7/527 , G06F7/544 , G06F7/38
CPC分类号： G06F7/5443 , G06F7/483
摘要： A floating point unit 10 provides a multiply-accumulate operation to determine a result B+(A*C). The multiplier 20 takes several processing cycles to determine the product (A*C). Whilst the multiplier 20 and its subsequent carry-save-adder 26 operate, an aligned value B' of the addend B is generated by an alignment-shifter 34. The aligned-addend B' may only partially overlap with the product (A*C) to which it is to be added using an adder 44. Any high-order-portion HOP of the aligned-addend B' that does not overlap with the product (A*C) must be subsequently concatenated with the output of the adder 44 that sums the product (A*C) with the overlapping portion of the aligned-addend B'. If the sum performed by the adder 44 generates a carry then it is an incremented version IHOP of the high-order-portion that should be concatenated with the output of the adder 44. This incremented-high-order-portion is generated by the adder 44 during otherwise idle processing cycles present due to the multiplier 20 operating over multiple cycles.
摘要翻译：浮点单元10提供乘积累运算以确定结果B +（A * C）。乘法器20需要几个处理周期来确定乘积（A * C）。虽然乘法器20及其随后的进位保存加法器26运行，加法器B的对准值B'由对准移位器34产生。对齐加法器B'可以仅部分地与产品重叠（A * C ），并且与乘积（A * C）不重叠的对齐加法器B'的任何高阶部分HOP必须随后与加法器44的输出连接将产品（A * C）与对齐加法器B'的重叠部分相加。如果由加法器44执行的和产生进位，则它是应该与加法器44的输出相连的高阶部分的递增版本IHOP。这个递增高阶部分由加法器在另外的空闲处理周期期间由于倍增器20在多个周期上操作而存在。

6. 发明授权

US6148314A Round increment in an adder circuit 有权
标题翻译：加法器电路中的加法
公开(公告)号：US6148314A
公开(公告)日：2000-11-14
申请号：US143614
申请日：1998-08-28
申请人： David Terrence Matheny , David Vivian Jaggar , David James Seal
发明人： David Terrence Matheny , David Vivian Jaggar , David James Seal
IPC分类号： G06F7/485 , G06F7/50 , G06F7/544
CPC分类号： G06F7/485 , G06F7/5443 , G06F7/49947
摘要： A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to subsequent normalization by a normalizer 60 and rounding by an incrementer 64. If an operation is performed that is immediately followed by an addition operation using the result of the preceding operation, then the normalized but unrounded sum is fed back to the adder 16 together with an indication of its rounding requirement. This rounding requirement can be performed by the adder 16 in parallel with the execution of the following addition by using the carry-in bit of the adder 16 to apply any increment required to rounding of the preceding result.
摘要翻译：描述了执行附加操作的浮点单元。浮点单元内的加法器16接收第一输入和第二输入以产生和。该总和经归一化器60随后归一化，并由加法器64进行舍入。如果使用前一操作的结果紧接着进行加法运算的操作，则将归一化但未被包围的和反馈到加法器16以及其舍入要求的指示。该加法器16可以通过使用加法器16的进位位并行执行后续加法来执行舍入要求，以应用对前一结果进行舍入所需的任何增量。

7. 发明授权

US07240144B2 Arbitration of data transfer requests 有权
标题翻译：仲裁数据传输请求
公开(公告)号：US07240144B2
公开(公告)日：2007-07-03
申请号：US10815961
申请日：2004-04-02
申请人： Tan Ba Tran , Gerard Richard Williams , David Terrence Matheny , David Walter Flynn
发明人： Tan Ba Tran , Gerard Richard Williams , David Terrence Matheny , David Walter Flynn
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/28
摘要： A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated with said data processor core; a data processing portion 12 operable to perform data processing operations; a read/write port 40 operable to transfer data from said processor core to at least two buses 75A, 75B said at least two buses being operable to provide data communication between said processor core 10 and said at least one memory 120, said at least one memory 120 comprising at least two portions 120A, 120B, each of said at least two buses 75A, 75B being operable to provide data access to respective ones of said at least two portions 120A, 120B; arbitration logic 110 associated with said read/write port 40; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least two buses providing access to said one portion of said at least one memory and to route a further data access request requesting access of data in a further portion of said at least one memory received from said data processing portion to a further one of said at least two buses providing access to said further portion of said at least one memory, said routing of said data access requests being performed during the same clock cycle.
摘要翻译：一种数据处理器核心10，包括：存储器访问接口部分30，可操作以在外部数据源与与所述数据处理器核心相关联的至少一个存储器120之间执行数据传输操作; 数据处理部分12，用于执行数据处理操作; 读/写端口40，其可操作以将数据从所述处理器核传输到至少两个总线75A，75B，所述至少两个总线可操作以在所述处理器核心10和所述至少一个存储器120之间提供数据通信，至少一个存储器120包括至少两个部分120A，120B，所述至少两个总线75A，75B中的每一个可操作以提供对所述至少两个部分120A，120B中的相应部分的数据访问; 与所述读/写端口40相关联的仲裁逻辑110; 其中所述仲裁逻辑可操作用于将请求数据访问的数据访问请求路由到从所述存储器访问接口接收的所述至少一个存储器的一部分中的数据访问到所述至少两个总线之一，提供对所述至少一个的所述一个部分的访问存储器，并且路由进一步的数据访问请求，请求从所述数据处理部分接收的所述至少一个存储器的另一部分中的数据访问到所述至少两个总线中的另一个，提供对所述至少一个存储器，所述数据访问请求的路由在相同的时钟周期期间执行。

8. 发明授权

US5646875A Denormalization system and method of operation 失效
标题翻译：非正规化系统和操作方法
公开(公告)号：US5646875A
公开(公告)日：1997-07-08
申请号：US394854
申请日：1995-02-27
申请人： Michael Preston Taborn , Steven Michael Burchfiel , David Terrence Matheny
发明人： Michael Preston Taborn , Steven Michael Burchfiel , David Terrence Matheny
IPC分类号： G06F7/57 , G06F7/38
CPC分类号： G06F7/483 , G06F7/49936
摘要： A system and method for denormalizing a floating point result is disclosed. Denormalized operands are capable of representing much smaller values than can be represented by a number normalized under the ANSI/IEEE standard 754-1985 that governs the representation of numbers in floating point notation to ensure uniformity among floating point notation users. The majority of results will be normalized operands and therefore the floating point unit pipeline is optimized to produce normalized results but contains wider exponent fields in order to represent values received as denormalized numbers. In order to return the result as a denormalized number with the smaller ANSI/IEEE exponent field, denormalization is accomplished by using the same pipeline resources by means of the floating point unit feedback path and uses one of the exponent equalizing alignment shifters and an incrementor in order to round the denormalized result. In this way, denormalized results can be provided without stopping the dispatching of instructions, without providing status bits in the register files and rename registers and without the hold signals often present in other floating point units to accomplish denormalization.
摘要翻译：公开了一种用于非标准化浮点结果的系统和方法。非归一化操作数能够表示比由ANSI / IEEE标准754-1985规范化的数字表示的值更小的值，该标准控制浮点符号中数字的表示，以确保浮点符号用户之间的一致性。大多数结果将是归一化操作数，因此浮点单元流水线被优化以产生归一化结果，但是包含较大的指数字段，以便表示以非正规化数字接收的值。为了以较小的ANSI / IEEE指数字段返回结果作为非规范化数字，通过利用浮点单元反馈路径使用相同的流水线资源来实现非规范化，并且使用指数均衡对准移位器和增量器之一为了减少非规范化结果。以这种方式，可以在不停止指令调度的情况下提供非规范化结果，而不在寄存器文件和重命名寄存器中提供状态位，并且不存在经常存在于其他浮点单元中的保持信号以实现非规范化。

9. 发明授权

US6108682A Division and/or square root calculating circuit 失效
标题翻译：分割和/或平方根计算电路
公开(公告)号：US6108682A
公开(公告)日：2000-08-22
申请号：US78722
申请日：1998-05-14
申请人： David Terrence Matheny
发明人： David Terrence Matheny
IPC分类号： G06F7/52 , G06F7/483 , G06F7/49 , G06F7/535 , G06F7/552
CPC分类号： G06F7/49
摘要： An iterative division and/or iterative square root circuit 20 uses quotient digits q.sub.j+1 within the calculation that are dependent upon the input divisor D or radicand A and current partial remainder or partial radicand P.sub.j for the cycle reached. As the input divisor D or radicand A is fixed throughout the calculation, the critical path through the iterative circuit may be speeded up by preselecting and storing a subset QC of quotient digit values using a primary quotient digit selecting circuit 18, 22 operating in dependence upon the divisor D or radicand A and independently of the partial remainder or partial radicand P.sub.j. Within the iterative circuit 20, the quotient digits q.sub.j+1 to be used for each cycle can then be selected from this subset QC by a secondary quotient digit selecting circuit 24 in dependence upon the partial remainder or partial radicand P.sub.j and independent of the divisor D or radicand A.
摘要翻译：迭代除法和/或迭代平方根电路20在计算中使用依赖于所达到的周期的输入除数D或者radicand A以及当前部分余数或部分radicand Pj的商数qj + 1。由于在整个计算过程中输入除数D或者radic A都是固定的，所以通过迭代电路的关键路径可以通过使用主商数字选择电路18,22预先选择和存储商数值的子集QC来加速，依赖于除数D或radicand A，并且独立于部分余数或部分radicand Pj。在迭代电路20内，然后可以根据部分余数或部分radicand Pj并且独立于除数D，由次级商数字选择电路24从该子集QC中选择要用于每个周期的商数qj + 1 或radicand A.

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