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1. 发明授权

US06216222B1 Handling exceptions in a pipelined data processing apparatus 失效
标题翻译：处理流水线数据处理设备中的异常
公开(公告)号：US06216222B1
公开(公告)日：2001-04-10
申请号：US09078595
申请日：1998-05-14
申请人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , Matthew Paul Elwood
发明人： Christopher Neal Hinds , David Vivian Jaggar , David Terrence Matheny , Matthew Paul Elwood
IPC分类号： G06F9302
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3867
摘要： A data processing apparatus and method is provided, the apparatus comprising an execution unit having a plurality of pipelined stages for executing instructions, such that a maximum of ‘n’ instructions can be being executed simultaneously within the execution unit. Further, a set of at least ‘n’ logical exception registers are provided, each exception register being capable of storing a number of exception attributes associated with an instruction for which an exception has been detected during execution by the execution unit. In the event of an exception being detected during execution of a first instruction, the execution unit is arranged to: (i) store in a first of said exception registers said exception attributes associated with said first instruction; and (ii) to continue executing any remaining instructions already in the pipelined stages at the time the exception was detected. The execution unit is further arranged to store in said exception registers the exception attributes associated with any of the remaining instructions for which an exception is detected during execution, whereby the exception attributes stored in the exception registers can be provided to an exception processing tool for use in recovering from any exceptions occurring during processing of said first instruction and said remaining instructions. By this approach, when the exception processing tool is invoked, then it can deal with any exceptions arising from the instructions executed by the pipeline, and the data processing apparatus can then continue with the next instruction, without the need to re-execute any of the instructions that were in the pipeline at the time the first exception was detected.
摘要翻译：提供了一种数据处理装置和方法，该装置包括具有多个流水线级的执行单元，用于执行指令，使得在执行单元内可以同时执行“n”个指令的最大值，此外，提供了至少“n”个逻辑异常寄存器，每个异常寄存器能够存储与由执行单元执行期间检测到异常的指令相关联的多个异常属性。在执行第一指令期间检测到异常的情况下，执行单元被配置为：（i）在所述异常寄存器的第一个中存储与所述第一指令相关联的异常属性; 和（ii）在检测到异常时继续执行已经在流水线阶段中的任何剩余指令。所述执行单元还被布置为在所述异常寄存器中存储与执行期间检测到异常的任何剩余指令相关联的异常属性，从而可以将异常寄存器中存储的异常属性提供给用于使用的异常处理工具在从所述第一指令和所述剩余指令的处理期间发生的任何异常中恢复。通过这种方法，当调用异常处理工具时，它可以处理由流水线执行的指令引起的任何异常，然后数据处理设备可以继续下一个指令，而不需要重新执行任何在检测到第一个异常时正在流水线中的指令。

2. 发明授权

US06332186B1 Vector register addressing 有权
标题翻译：向量寄存器寻址
公开(公告)号：US06332186B1
公开(公告)日：2001-12-18
申请号：US09143449
申请日：1998-08-28
申请人： Matthew Paul Elwood , Christopher Neal Hinds
发明人： Matthew Paul Elwood , Christopher Neal Hinds
IPC分类号： G06F1200
CPC分类号： G06F9/30098 , G06F7/483 , G06F7/49957 , G06F7/5443 , G06F9/30087 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/345 , G06F9/3455 , G06F9/3838 , G06F9/3877
摘要： A floating point unit 26 is provided with a register bank 38 comprising 32 registers that may be used as either vector registers V or scalar registers S. Data values are transferred between memory 30 and the registers within the register bank 38 using contiguous block memory access instructions. Vector processing instructions specify a sequence of processing operations to be performed upon data values within a sequence of registers. The register address is incremented between each operation by an amount controlled by a stride value. Accordingly, the register address can be incremented by values such as 0, 1, 2 or 4 between each iteration. This provides a mechanism for retaining block memory access instructions to contiguous memory addresses whilst supporting vector matrix and/or complex operations in which the data values needed for each iteration are not adjacent to one another in the memory 30.
摘要翻译：浮点单元26设置有寄存器组38，寄存器组38包括可用作向量寄存器V或标量寄存器S的32个寄存器。数据值使用连续块存储器访问指令在存储器30和寄存器组38内的寄存器之间传送。向量处理指令指定要对寄存器序列内的数据值执行的处理操作序列。寄存器地址在每个操作之间递增由步幅值控制的量。因此，寄存器地址可以在每次迭代之间增加诸如0,1,2或4之间的值。这提供了一种用于将块存储器访问指令保持到连续存储器地址的机制，同时支持向量矩阵和/或复合操作，其中每个迭代所需的数据值在存储器30中彼此不相邻。

3. 发明授权

US07447885B2 Reading prediction outcomes within a branch prediction mechanism 有权
标题翻译：在分支预测机制中阅读预测结果
公开(公告)号：US07447885B2
公开(公告)日：2008-11-04
申请号：US11109956
申请日：2005-04-20
申请人： Matthew Paul Elwood
发明人： Matthew Paul Elwood
IPC分类号： G06F9/00
CPC分类号： G06F9/3848
摘要： A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and stored into a prediction value store. The one or more prediction values to be used with a potential branch instruction are selected from the prediction values store using a multiplexer switched by a branch predicting portion of a fetch address. The history buffer is only read when the history value changes whereas the prediction values store is read each time a potential branch instruction is identified requiting a prediction value to be associated with it. The reduced duty cycle of the history buffer saves power.
摘要翻译：分支预测机构包括历史值寄存器，该历史值寄存器存储历史值，该历史值被用于寻址到将多个预测值从其读取并存储到预测值存储中的历史缓冲器中。使用由提取地址的分支预测部分切换的多路复用器从预测值存储中选择要用于潜在分支指令的一个或多个预测值。仅当历史值改变时才读取历史缓冲器，而每当潜在的分支指令被识别为需要与之相关联的预测值时，就读取预测值存储。历史缓冲区的占空比减少可以节省电力。

4. 发明授权

US07447882B2 Context switching within a data processing system having a branch prediction mechanism 有权
标题翻译：具有分支预测机制的数据处理系统内的上下文切换
公开(公告)号：US07447882B2
公开(公告)日：2008-11-04
申请号：US11109957
申请日：2005-04-20
申请人： Matthew Paul Elwood
发明人： Matthew Paul Elwood
IPC分类号： G06F9/00
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/3806 , G06F9/3844 , G06F9/3861
摘要： A branch target buffer is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries within the branch target buffer and those individual entries are invalidated.
摘要翻译：提供了一个分支目标缓冲区，其在虚拟地址系统内保持其条目跨越上下文切换。检测到分支目标缓冲区内的各个条目的分支错误预测，并且这些单个条目无效。

5. 发明授权

US07793078B2 Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding 有权
标题翻译：多指令集数据处理系统具有第一指令集的条件转移指令和共享相同指令编码的第二指令集
公开(公告)号：US07793078B2
公开(公告)日：2010-09-07
申请号：US11095655
申请日：2005-04-01
申请人： Matthew Paul Elwood , David John Butcher , Richard Roy Grisenthwaite
发明人： Matthew Paul Elwood , David John Butcher , Richard Roy Grisenthwaite
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/30072 , G06F9/30149 , G06F9/30189 , G06F9/30196 , G06F9/3844
摘要： A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditional branch instructions provided within the two different instruction sets are arranged to use the same instruction encoding.
摘要翻译：数据处理系统可在第一状态下操作，以使用具有第一指令集编码的第一指令集。数据处理系统还可在第二状态下操作以使用具有第二指令编码的第二指令集。在两个不同的指令集中提供的条件转移指令被设置为使用相同的指令编码。

6. 发明授权

US06304963B1 Handling exceptions occuring during processing of vector instructions 有权
标题翻译：处理向量指令处理过程中处理异常
公开(公告)号：US06304963B1
公开(公告)日：2001-10-16
申请号：US09144175
申请日：1998-08-31
申请人： Matthew Paul Elwood
发明人： Matthew Paul Elwood
IPC分类号： G06F900
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3867
摘要： The data processing apparatus and method comprises an instruction decoder for decoding a vector instruction representing a sequence of data processing operations, and an execution unit comprising a plurality of pipelined stages for executing said sequence of data processing operations. The execution unit includes exception determination logic for determining, as each instruction enters a predetermined pipelined stage, whether that data processing operation is an exceptional operation matching predetermined exception criteria, the execution unit being arranged to halt processing of said exceptional operation. Further, an exception register is provided for storing exception attributes relating to said exceptional operation, said exception attributes indicating which data processing operation in said sequence has been determined to be said exceptional operation. This enables the exception attributes stored in the exception register to be provided to an exception processing tool for use in handling said exceptional operation. By this approach, it is possible for an exception processing tool to be used to handle the specific exceptional operation that has given rise to the exception condition, rather than providing the entire vector instruction for handling by the exception processing tool. Further, since the whole vector instruction does not need to be handled by an exception processing tool in the event of an exception being detected, it is possible for the registers holding data values associated with a particular data processing operation in the sequence to be released for use by subsequent instructions as soon as execution of that data processing operation has completed, rather than having to ensure that those registers are “locked” until the entire vector instruction has completed.
摘要翻译：数据处理装置和方法包括用于对表示数据处理操作序列的矢量指令进行解码的指令解码器，以及包括用于执行所述数据处理操作序列的多个流水线级的执行单元。执行单元包括异常确定逻辑，用于当每个指令进入预定流水线阶段时确定该数据处理操作是否是与预定异常标准相匹配的异常操作，执行单元被布置为停止所述异常操作的处理。此外，提供了用于存储与所述异常操作有关的异常属性的异常寄存器，所述异常属性指示所述序列中的哪个数据处理操作已被确定为所述异常操作。这使得将存储在异常寄存器中的异常属性提供给用于处理所述异常操作的异常处理工具。通过这种方法，可以使用异常处理工具来处理引起异常条件的特定异常操作，而不是提供用于异常处理工具处理的整个向量指令。此外，由于在检测到异常的情况下整个向量指令不需要被异常处理工具处理，所以可以将与序列中的特定数据处理操作相关联的数据值的寄存器释放以供一旦该数据处理操作的执行完成，则由后续指令使用，而不必确保这些寄存器被“锁定”，直到整个向量指令完成。

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